Patents Assigned to ADRC. CO. KR
  • Patent number: 11786929
    Abstract: The present disclosure provides a spray coater including a spray nozzle unit having at least one spray nozzle and configured to spray a coating material, a spray nozzle transfer unit configured to control a position of the spray nozzle unit by operating a transfer block, on which the spray nozzle unit is mounted, at least in a planar direction, a substrate seating unit positioned below the spray nozzle unit and configured such that a substrate, which is subjected to coating, is seated thereon, a substrate carrier configured to accommodate the substrate before the substrate is coated and accommodate the substrate after the substrate is coated, and a robot arm configured to unload the substrate from the substrate carrier and provide the substrate to the substrate seating unit before the substrate is coated or unload the substrate from the substrate seating unit and load the substrate on the substrate carrier after the substrate is coated.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 17, 2023
    Assignee: ADRC. CO. KR
    Inventor: Jin Jang
  • Patent number: 11682680
    Abstract: Disclosed are a crystalline oxide semiconductor thin film including a crystalline oxide semiconductor including indium, gallium, and tin, the crystalline oxide semiconductor exhibiting a (009) diffraction peak in an X-ray diffraction spectrum, and a method of forming the same, a thin film transistor and a method of manufacturing the same, a display panel, and an electronic device.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 20, 2023
    Assignee: ADRC. CO. KR
    Inventors: Soon Ho Choi, Chae Yeon Hwang, Suhui Lee
  • Patent number: 11663978
    Abstract: The present invention relates to a driving circuit including stages for supplying signals. The respective stages may include: a first LTPO transistor including a first transistor that is a low-temperature polycrystalline silicon thin film transistor (LTPS TFT) and a second transistor that is an oxide TFT; and a second LTPO transistor including a third transistor that is an LTPS TFT and a fourth transistor that is an oxide TFT. A first end of the first LTPO transistor may be connected to a gate of the second LTPO transistor, and voltages of signals corresponding to the respective stages from among the signals may be a voltage at a first end of the second LTPO transistor.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: May 30, 2023
    Assignee: ADRC. CO. KR
    Inventors: Jin Jang, Jun Hyuk Cheon, Junyeong Kim, Suhui Lee, Yuanfeng Chen, Mohammad Masum Billah
  • Patent number: 11616086
    Abstract: A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the f
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 28, 2023
    Assignee: ADRC. CO. KR
    Inventors: Duk Young Jeong, Chae Yeon Hwang, Dong Gyu Eo
  • Patent number: 11587952
    Abstract: A thin film transistor according to an exemplary embodiment includes: a substrate; a semiconductor layer disposed on the substrate and including a channel region, and an input region and an output region disposed on both sides of the channel region and doped with an impurity; a buffer layer disposed between the substrate and the semiconductor layer; a control electrode overlapping the semiconductor layer; a gate insulation layer disposed between the semiconductor layer and the control electrode; and an input electrode connected to the input region and an output electrode connected to the output region, wherein the semiconductor layer includes polysilicon and is crystallized by a blue laser scan.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: February 21, 2023
    Assignee: ADRC. CO. KR
    Inventors: Youngbin Do, Chae Yeon Hwang