Patents Assigned to Advance Micro Devices
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Publication number: 20240333519Abstract: The disclosed computing device can include super flow control unit (flit) generation circuitry configured to generate a super flit containing two or more flits having two or more requests embedded therein, wherein the two or more requests have the same destination node identifiers and the super flit has a variable size based on a flit size and a number of existing requests in a source node that target a same destination node. The device can additionally include authentication circuitry configured to append a message authentication code to a last flit of the super flit. The device can also include communication circuitry configured to send the super flit to a network switch configured to route the super flit to a destination node corresponding to the same destination node identifiers. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov, Donald Matthews, Jr., Srilatha Manne
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Publication number: 20240329838Abstract: A data processing system includes a data processor having a memory controller, and a memory. The memory is coupled to the memory controller and is for reading and writing data synchronously with respect to a clock signal. The memory includes a sensor circuit that is responsive to a control signal to output a measured value without using the clock signal.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Aaron D. Willey
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Publication number: 20240330134Abstract: A system that includes at least a system memory, a chipset link, and a chipset attached memory is powered down. A boot-up process is loaded in the chipset attached memory. The boot-up process is performed for the system, via the chipset link, by the chipset attached memory. The boot-up process includes loading one or more memory testing applications. The system memory is tested using the one or more memory testing applications loaded by the chipset attached memory.Type: ApplicationFiled: March 27, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
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Patent number: 12106418Abstract: Devices, systems, and methods for sampling partially resident texture data. An instruction which includes a residency map descriptor is received. The instruction is executed to retrieve partially resident texture data from a mipmap stored in a memory based on the residency map descriptor. The residency map descriptor includes a residency map.Type: GrantFiled: October 29, 2020Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Fataneh F. Ghodrat, Michael Lee Grossfeld, Kevin Warren Furrow
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Patent number: 12105957Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.Type: GrantFiled: December 23, 2022Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez
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Patent number: 12105646Abstract: A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to the allotted virtual queues and enables the return queue for arbitration. When the return queue is enabled for arbitration, the processor reads out the data written to the allocated virtual queues, processes the read out data, and provides the processed data to a processing pipeline.Type: GrantFiled: December 1, 2021Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Fataneh Ghodrat
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Patent number: 12107076Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.Type: GrantFiled: December 28, 2021Date of Patent: October 1, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wonjun Jung, Jasmeet Singh Narang, Tyrone Huang, Christopher Klement, Alan D. Smith, Edward Chang, John Wuu
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Patent number: 12105666Abstract: A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.Type: GrantFiled: April 19, 2021Date of Patent: October 1, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Shijie Che, Wentao Xu, Randall Brown, Vaibhav Amarayya Hiremath, Manuchehr Taghi-Loo
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Patent number: 12105952Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.Type: GrantFiled: September 30, 2022Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Vydhyanathan Kalyanasundharam
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Patent number: 12105139Abstract: A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.Type: GrantFiled: December 29, 2021Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Vidyashankar Viswanathan, Richard E. George, Michael Y. Chow
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Publication number: 20240321702Abstract: A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.Inventors: Yan Wang, Kevin Gillespie, Samuel Naffziger, Richard Schultz, Raja Swaminathan, Omar Zia, John Wuu
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Publication number: 20240321668Abstract: A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.Inventors: Thomas D. Burd, Gabriel H. Loh, John Wuu, Kevin Gillespie, Raja Swaminathan, Richard Schultz, Samuel Naffziger, Srividhya Venkataraman, Yan Wang
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Publication number: 20240319911Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.Type: ApplicationFiled: May 31, 2024Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vamsee Reddy Kommareddy, SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov
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Publication number: 20240321706Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: William George En, Samuel Naffziger, Regina T. Schmidt, Omar Zia, John Wuu
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Publication number: 20240319903Abstract: Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read request using the contents on the chipset attached memory. Servicing the memory requests further includes communicating a write request to the system memory and to the chipset attached memory.Type: ApplicationFiled: March 22, 2023Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Jerry Anton Ahrens, Anil Harwani, Joshua Taylor Knight, Grant Evan Ley, Amitabh Mehra
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Publication number: 20240319910Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.Type: ApplicationFiled: May 31, 2024Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vamsee Reddy Kommareddy, SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov
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Publication number: 20240324248Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: John Wuu, Kevin Gillespie, Samuel Naffziger, Spence Oliver, Rajit Seahra, Regina T. Schmidt, Raja Swaminathan, Omar Zia
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Publication number: 20240321827Abstract: A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.Inventors: Omar Zia, Thomas D Burd, Kevin Gillespie, Samuel Naffziger, Richard Schultz, Raja Swaminathan, Srividhya Venkataraman, Yan Wang, John Wuu
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Publication number: 20240324247Abstract: A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 25, 2023Publication date: September 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Samuel Naffziger, William George En, John Wuu
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Patent number: 12100660Abstract: A system and method for creating layout for standard cells are described. In various implementations, a semiconductor fabrication process (or process) forms a power signal route in a same metal zero track reserved for power rails. The process forms a contact layer with inserted spacing underneath the power signal route. Along the track, this contact layer has physical contact with the power signal route with a first distance greater than a width of any signal route in any metal layer orthogonal to the power signal route, and has no physical contact with the power signal route with a second distance greater than the width. One or more signal routes in the local interconnect layer are routed through this spacing. Without this spacing, signals would be routed through this area using the metal one layer, which increases signal congestion.Type: GrantFiled: October 4, 2021Date of Patent: September 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Partha Pratim Ghosh, Pratap Kumar Das, Prasanth M
