Patents Assigned to Advance Micro Devices
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Patent number: 12242325Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.Type: GrantFiled: March 30, 2022Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Patent number: 12242407Abstract: An exemplary data fabric device comprises a first traffic moderator configured to receive traffic destined for a specific endpoint accessible via a plurality of data paths and divert the traffic from a first data path included in the data paths to a second data path included in the data paths. The exemplary data fabric device also comprises a first interconnect controller that resides within the second data path and is configured to forward the traffic to the specific endpoint via a first communication link to test a functionality of the first communication link. Various other apparatuses, systems, and methods are also disclosed.Type: GrantFiled: November 8, 2022Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Samuel Abraham Lipson, Eric Christopher Morton, Bryan P. Broussard, Vydhyanathan Kalyanasundharam
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Patent number: 12242384Abstract: Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some implementations, the other data is prefetched to the cache memory based on a total of a compressed size of the first data and a compressed size of the other data being less than a threshold size. In some implementations, the other data is not prefetched to the cache memory based on the other data being uncompressed.Type: GrantFiled: January 27, 2023Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Pazhani Pillai, Harish Kumar Kovalam Rajendran
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Patent number: 12243578Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.Type: GrantFiled: December 20, 2023Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Karthik Gopalakrishnan, Tsun Ho Liu
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Patent number: 12235708Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.Type: GrantFiled: September 23, 2021Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry, Mihir Shaileshbhai Doctor
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Patent number: 12236555Abstract: A method and processing device for image demosaicing is provided. The processing device comprises memory and a processor. The processor is configured to, for a pixel of a Bayer image which filters an acquired image using three color components, determine directional color difference weightings in a horizontal direction and a vertical direction, determine a color difference between the first color component and the second color component and a color difference between the second color component and the third color component based on the directional color difference weightings, interpolate a color value of the pixel from the one color component and the color differences and provide a color image for display.Type: GrantFiled: December 23, 2021Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Linwei Yu, Jiangli Ye, Yang Ling, Hui Zhou
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Patent number: 12235756Abstract: Near-memory compute elements perform memory operations and temporarily store at least a portion of address information for the memory operations in local storage. A broadcast memory command is then issued to the near-memory compute elements that causes the near-memory compute elements to perform a subsequent memory operation using their respective address information stored in the local storage. This allows a single broadcast memory command to be used to perform memory operations across multiple memory elements, such as DRAM banks, using bank-specific address information. In one implementation, the approach is used to process workloads with irregular updates to memory while consuming less command bus bandwidth than conventional approaches. Implementations include using conditional flags to selectively designate address information in local storage that is to be processed with the broadcast memory command.Type: GrantFiled: December 21, 2021Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Shaizeen Aga, Johnathan Alsop, Nuwan Jayasena
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Patent number: 12236109Abstract: A cloud computing system includes cloud orchestrator circuitry and fabric manager circuitry. The cloud orchestrator circuitry receives an input application and determines a task graph, a data graph, and a function popularity heap parameter for the input application. The task graph comprises an indication of function interdependency of functions of the input application, the data graph comprises an indication of data interdependency of the functions, and the function popularity heap parameter corresponds to a re-usability index for the functions. The fabric manager circuitry allocate a first programmable integrated circuit (IC) device to perform a first function of the input application based on the task graph, the data graph, and the function popularity heap parameter.Type: GrantFiled: May 24, 2023Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Pratik Mishra, Sergey Blagodurov, Atul Kumar Sujayendra Sandur
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Patent number: 12236134Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.Type: GrantFiled: September 27, 2022Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Mahzabeen Islam, Shaizeen Dilawarhusen Aga, Johnathan Robert Alsop, Mohamed Assem Abd ElMohsen Ibrahim, Nuwan S Jayasena
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Patent number: 12237026Abstract: The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline through the drain of the transistor for local bitline sensing. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: November 7, 2022Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Vaibhav Anand Srivastava, Pankaj Kumar
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Patent number: 12236529Abstract: Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.Type: GrantFiled: December 27, 2021Date of Patent: February 25, 2025Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Christopher J. Brennan, Randy Wayne Ramsey, Nishank Pathak, Ricky Wai Yeung Iu, Jimshed Mirza, Anthony Chan
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Publication number: 20250061071Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.Type: ApplicationFiled: October 8, 2024Publication date: February 20, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Hideki Kanayama, YuBin Yao
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Patent number: 12229563Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: June 30, 2022Date of Patent: February 18, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Sree Harsha Kosuru, Eric Dixon, Erik Swanson, Michael Estlick, Patrick Michael Lowry
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Patent number: 12231120Abstract: A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.Type: GrantFiled: June 30, 2022Date of Patent: February 18, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Jagadeesh Anathahalli Singrigowda, Girish A S, Aniket Bharat Waghide, Prasant Kumar Vallur
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Patent number: 12229570Abstract: Block data load with transpose techniques are described. In one example, an input is received, at a control unit, specifying an instruction to load a block of data to at least one memory module using a transpose operation. Responsive to the receiving the input by the control unit, the block of data is caused to be loaded to the at least one memory module by transposing the block of data to form a transposed block of data and storing the transposed block of data in the at least one memory.Type: GrantFiled: September 25, 2022Date of Patent: February 18, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Bin He, Michael John Mantor, Brian Emberling, Liang Huang, Chao Liu
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Patent number: 12222797Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: December 19, 2022Date of Patent: February 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: James Mossman, Robert Cohen, Sudherssen Kalaiselvan, Tzu-Wei Lin
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Patent number: 12225299Abstract: A system for automatic image band detection includes concurrently capturing a first image of a scene with a first camera having a first exposure time and a second image of the scene with a second camera having a second exposure time. The system detects image banding for one of the first camera and the second camera based on the first image and the second image.Type: GrantFiled: December 28, 2021Date of Patent: February 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Po-Min Wang, MuFan Yen
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Publication number: 20250044966Abstract: The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: July 31, 2023Publication date: February 6, 2025Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Nicholas Carmine DeFiore, Sridhar Varadharajulu Gada, James R. Magro, Michael L. Choate, Wayne Paul Rodrigue, NrusimhaVamsi Krishna Godavarti, Robert Gentile, Roozbeh Paribakht, Anwar Kashem
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Patent number: 12217059Abstract: The disclosed device a controller that sets an iteration counter for a loop based on an iteration value read from a loop iteration instruction for the loop. The controller also updates the iteration counter based on a number of times a loop heading instruction for the loop is decoded. When the iteration counter reaches an end value, the controller selects a not taken identifier for the loop to be fetched, to avoid a branch misprediction. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: March 30, 2023Date of Patent: February 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Toufic Freij, Gabriel H. Loh, Onur Kayiran
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Patent number: 12216590Abstract: A cache controller of a processing system implementing a non-uniform memory architecture (NUMA) adjusts a cache replacement priority of local and non-local data stored at a cache based on a cache replacement policy. Local data is data that is accessed by the cache via a local memory channel and non-local data is data that is accessed by the cache via a non-local memory channel. The cache controller assigns priorities to local and non-local data stored at the cache based on a cache replacement policy and selects data for replacement at the cache based, at least in part, on the assigned priorities.Type: GrantFiled: June 9, 2023Date of Patent: February 4, 2025Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Saurabh Sharma, Hashem Hashemi, Guennadi Riguer
