Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.

Abstract: The present invention relates to a silicon chip including a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit.

Abstract: A stacked flip-chip package comprises a substrate having an opening, a back-to-face chip module, and an encapsulant. The back-to-face chip module is attached to the substrate and encapsulated by the encapsulant. The back-to-face chip module includes a first chip and a second chip. The first chip has a first active surface and a first back surface. Redistributed traces are formed on the first back surface. The second chip is flip-chip mounted on the first back surface of the first chip and electrically connected to the redistributed traces. A plurality of bumps connect the redistributed traces to the top surface of the substrate. Thus the second chip can be accommodated inside the opening and the redistributed traces are electrically connected to the second chip and the substrate so as to achieve fine pitch flip-chip mounting and improve the electrical performance and heat dissipation efficiency for the back-to-face chip module.