Abstract: A sense amplifier includes cross-coupled latch has a PMOS bias transistor for selectively connecting the cross-coupled latch to a supply voltage and has an NMOS bias transistor for selectively connecting the cross-coupled latch to ground potential. The conductivity of the PMOS bias transistor is controlled by a first bias signal having a magnitude dependent upon the supply voltage and, in a similar manner, the conductivity of the NMOS bias transistor is controlled by a second bias signal also having a magnitude dependent upon the supply voltage. When the supply voltage exceeds a predetermined level, the first and second bias signals are of respective magnitudes so as to slowly turn on the PMOS and NMOS bias signals. In this manner, the current flow is gradually increased to the sense circuit at high voltages, thereby minimizing noise and power consumption.

Abstract: A DRAM includes a data input buffer having a first input terminal coupled to data I/O pins, a second input terminal coupled to a column address buffer, a third input terminal coupled to a column address strobe buffer, and an output terminal coupled to a column decoder. When reading a selected cell of the DRAM, the first row address and the first column address are latched on the falling edge of the row address strobe signal from the address input pins into a row address buffer and from the I/O pins into the data input buffer, respectively, of the DRAM. While the row address is decoded and used to select a row of memory cells of the DRAM, the column address is decoded and used to select one of the cells from the selected row. Data corresponding to the selected cell is forwarded to the I/O pins on the first falling edge of the column address strobe signal.