Patents Assigned to Advanced Chip Engineering Technology Inc.
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Patent number: 8178963Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die disposed within the die receiving through hole; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.Type: GrantFiled: January 3, 2007Date of Patent: May 15, 2012Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen-Kun Yang
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Patent number: 8178964Abstract: A structure of a semiconductor device package having a substrate with a die receiving through hole, a connecting through hole structure and a contact pad. A die is disposed within the die receiving through hole. A surrounding material is formed under the die and filled in the gap between the die and the sidewall of the die receiving though hole. Dielectric layers are formed on the both side surface of the die and the substrate. Re-distribution layers (RDL) are formed on the dielectric layers and coupled to the contact pads. Protection layers are formed over the RDLs.Type: GrantFiled: March 30, 2007Date of Patent: May 15, 2012Assignee: Advanced Chip Engineering Technology, Inc.Inventor: Wen-Kun Yang
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Patent number: 8058102Abstract: The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.Type: GrantFiled: November 10, 2009Date of Patent: November 15, 2011Assignee: Advanced Chip Engineering Technology Inc.Inventors: Diann-Fang Lin, Yu-Shan Hu
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Patent number: 7985626Abstract: A manufacturing method of placing dice for a wafer level package comprises placing a plurality of dice on an elastic material, which is formed on a first base, and the elastic material of the present invention has viscosity in a first condition to adhere the plurality of dice; forming an adhesive material on a second base; adhering the plurality of dice on the adhesive material of the second base; and stripping the plurality of dice from the elastic material in a second condition.Type: GrantFiled: June 20, 2005Date of Patent: July 26, 2011Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-li Chen
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Patent number: 7911044Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.Type: GrantFiled: December 29, 2006Date of Patent: March 22, 2011Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Chun-Hui Yu, Chihwei Lin
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Patent number: 7884464Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.Type: GrantFiled: June 27, 2006Date of Patent: February 8, 2011Assignee: Advanced Chip Engineering Technologies Inc.Inventors: Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, Kou-Ning Chiang
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Patent number: 7863105Abstract: An image sensor package comprises a substrate, a chip mounted over the substrate. A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the micro lens. A redistributed conductive layer is formed over the molding material to connect to a pad of the chip. Metal pads are formed on via structure as connecting points with PCB. A cover layer is formed over the substrate to isolate the metal pads.Type: GrantFiled: May 8, 2008Date of Patent: January 4, 2011Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang
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Patent number: 7812434Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.Type: GrantFiled: January 3, 2007Date of Patent: October 12, 2010Assignee: Advanced Chip Engineering Technology IncInventor: Wen-Kun Yang
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Patent number: 7763494Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.Type: GrantFiled: July 9, 2008Date of Patent: July 27, 2010Assignee: Advanced Chip Engineering Technology, Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin
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Patent number: 7687923Abstract: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation.Type: GrantFiled: November 1, 2007Date of Patent: March 30, 2010Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Hsien-Wen Hsu
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Patent number: 7667318Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.Type: GrantFiled: October 22, 2008Date of Patent: February 23, 2010Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
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Patent number: 7655501Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.Type: GrantFiled: June 18, 2008Date of Patent: February 2, 2010Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Tung-Chuan Wang, Chao-Nan Chou, Chih-Wei Lin
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Patent number: 7566854Abstract: The present invention provides an image sensor module. The image sensor module has a die formed on a substrate, the die having a micro lens area, a lens holder formed on the substrate and over the die, a lens formed in the lens holder. A filter is formed within the lens holder and between the lens and the die, and at least one passive device formed on the substrate and covered within the lens holder. Conductive bumps or LGA (leadless grid array) are formed on the bottom surface of the substrate.Type: GrantFiled: December 8, 2006Date of Patent: July 28, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang
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Patent number: 7557437Abstract: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: GrantFiled: November 28, 2007Date of Patent: July 7, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
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Patent number: 7534632Abstract: A method for circuit inspection comprises steps of providing a substrate having a conductive line; and forming a metal layer on at least the conductive layer to increase a contrast between the conductive layer and adjacent area for the circuit inspection. The method further comprising removing the metal layer. The metal layer is removed by a mixture of nitric acid, hydrogen peroxide and fluoride boric acid. The metal includes Silver, Nickel or Tin. The deposit metal can be removed by inter diffusion and form intermetallic compounds (for example Cu6Sn5) into the under laying conducting line.Type: GrantFiled: February 20, 2007Date of Patent: May 19, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Yu-Shan Hu, Dyi-Chung Hu
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Patent number: 7525139Abstract: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.Type: GrantFiled: December 29, 2004Date of Patent: April 28, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Chin-Chen Yang, Wen-Ping Yang, Wen-Bin Sun, Chao-nan Chou, His-Ying Yuan, Jui-Hsien Chang
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Patent number: 7525185Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate.Type: GrantFiled: March 19, 2007Date of Patent: April 28, 2009Assignee: Advanced Chip Engineering Technology, Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin, Tung-Chuan Wang, Hsien-Wen Hsu, Chih-Ming Chen
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Patent number: 7514767Abstract: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type wafer level package. Moreover, the die may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: GrantFiled: July 7, 2006Date of Patent: April 7, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen-Kun Yang
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Patent number: 7501310Abstract: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.Type: GrantFiled: November 27, 2007Date of Patent: March 10, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Pin Yang
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Patent number: 7498646Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality of solder balls is attached to the metal alloy base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dice. The lens holder is placed in the flexible printed circuits (F.P.C.), and the flexible printed circuits (F.P.C.) has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dice. Moreover, the image sensor dice may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: GrantFiled: July 19, 2006Date of Patent: March 3, 2009Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen Kun Yang, Wen Pin Yang