Abstract: A direct memory access controller controls many direct memory access ports using a token passing scheme. The system multiplexes the port's accesses to external random access memory by daisy-chaining a loop of direct access memory ports and passing the token around to each port. Once a port receives the token it may request as many random access memory accesses as it requires. These accesses may be either read operations or write operations with both using the same multiplexed data bus. The latency inherent in reading an external RAM causes no loss in the access efficiency. When the port has completed its data transfer or if the port does not require a data transfer, the token is passed to the next direct memory access port for its data transfer. The token is passed around to all connected ports until all have had an opportunity to complete any memory transfers which they required. Each port is identical except for a binary identification code that is used to represent each port.

Abstract: An adaptive lossless data compression system with systolic string matching logic performs compression and decompression at the maximum rate of one symbol per clock cycle. The adaptive data compression system uses an improvement of the LZ1 algorithm. A content addressable memory (CAM) is used to store the last n input symbols. The CAM is stationary, stored data is not shifted throughout the CAM, but rather the CAM is used as a circular queue controlled by a Write Address Pointer Counter (WREN). During a compression operation, a new input symbol may be written to the CAM on each clock cycle, while simultaneously the rest of the CAM is searched for the input symbol. Associated with each word of the CAM array is a String Match State Machine (SMSM) and, an address logic module (ALM). These modules detect the occurrence of strings stored in the CAM array that match the current input string and report the address of the longest matching string nearest to the Write Address Pointer.