Abstract: Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.

Abstract: A processor and corresponding method are described including cores having a thread set allocated based on a pre-set implementation order, and a controller configured to receive scheduling information determined based on an implementation pattern regarding the allocated thread set from one of the cores and transmit the scheduling information to another of the cores. The one of cores determines the scheduling information according to characteristics of an application when implementation of the thread set is completed. Each of the cores re-determines an implementation order regarding the allocated thread set based on the determined scheduling information.

Abstract: Provided is a video encoding apparatus, including a signal separator to separate a differential image block into a first domain and a second domain, based on a boundary line included in the differential image block, the differential image block indicating a difference between an original image and a prediction image with respect to the original image, a transform encoder to perform a transform encoding with respect to the first domain using a discrete cosine transform (DCT), a quantization unit to quantize an output of the transform encoding unit in a frequency domain, a space domain quantization unit to quantize the second domain in a space domain, and an entropy encoder to perform an entropy encoding using outputs of the quantization unit and the space domain quantization unit.

Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The coding unit (CU) blocks are divided into sub-CU blocks. The sub-CU blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of a CU block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.

Abstract: A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.

Abstract: The present invention relates to a cell coating method using a compound including a gallate group, and a lanthanoid metal salt or transition metal salt. According to the cell coating method of the present invention, a cell having a surface coated with a nanoshell prepared by this method is stably protected from external environmental stimulus such as light irradiation, and silver nanoparticles, and the coating is degraded as necessary without damaging the cell.

Abstract: Disclosed are a hardware-based selective security apparatus and a security method using the same. The security apparatus according to an embodiment of the present invention includes: a transistor including a source electrode, a drain electrode, and a gate electrode composed of at least two electrodes; and a controller which selectively sets a security level 1 or a security level 2 by controlling a magnitude of a voltage which is applied to the gate electrode. According to the present invention, since there is no necessity of an additional space for a separate chip required by an existing hardware based security method, it is possible to obtain a recoverable hardware based security method which uses spaces usefully and has economic efficiency. Also, a recoverable security level and an irrecoverable security level are selectively applied, so that it is possible to implement an enhanced hardware-based security method.

Abstract: A waveguide of a 3D interconnection structure and an optical data bus system of a 3D interconnection structure using the same are provided. The waveguide includes a main waveguide which is formed in a predetermined direction and at least one branch waveguide which connects to the main waveguide to form a predetermined angle, wherein the at least one branch waveguide branches an optical signal, which is propagated in the main waveguide, at a predetermined rate.

Abstract: Disclosed is a method of manufacturing a colorless transparent polyimide film having impregnated glass fabric, wherein the surface of the polyimide film substrate having impregnated glass fabric is flattened by two flattening steps using a roll-to-roll process, thereby solving problems with an increase in surface roughness of the polyimide substrate when manufacturing the polyimide film having impregnated glass fabric in order to enhance thermal and mechanical properties of a film for use in flexible display substrates and in cover windows for flat panel displays and mobile phones.

Abstract: This disclosure relates to a method of manufacturing n-doped graphene and an electrical component using ammonium fluoride (NH4F), and to graphene and an electrical component thereby. An example method of manufacturing n-doped graphene includes (a) preparing graphene and ammonium fluoride (NH4F); and (b) exposing the graphene to the ammonium fluoride (NH4F), wherein through (b), a fluorine layer is formed on part or all of upper and lower surfaces of a graphene layer, and ammonium ions are physisorbed to part or all of the upper and lower surfaces of the graphene layer or defects between carbon atoms of the graphene layer, thereby maintaining or further improving superior electrical properties of graphene including charge mobility while performing n-doping of graphene.

Abstract: A method of cooperative multi-antenna communication between a base station and node existing in a wireless network is provided. A cooperative multi-antenna communication method includes receiving data from at least one node of a node group that receives data from a base station, performing multiple input multiple output (MIMO) signal processing with respect to the received data, the MIMO signal processing indicating signal processing performed in a receiving end of a MIMO system, and transmitting the signal processed data to at least one target node.

Abstract: A method for adjusting a beam pattern in a beam pattern adjusting apparatus in a communication system supporting a Beam Division Multiple Access (BDMA) scheme is provided. The method includes determining whether a Voltage Standing Wave Ratio (VSWR) value for each antenna included in an antenna array included in the beam pattern adjusting apparatus is greater than or equal to a threshold VSWR value, if it is determined that an antenna of the antenna array has a VSWR value that is greater than or equal to the threshold VSWR, detecting whether each of the antenna elements is operable, and if it is determined that at least one of the antennas is inoperable, adjusting a beam pattern of at least one of the antennas that is operable.

Abstract: The present invention provides a power gain-boosting technique for an amplifier in order to compensate for the decrease of Gmag in a transistor at high frequencies. A power gain-boosting technique of the present invention comprises the steps of: finding the Maximum Unilateral Gain or Mason's Invariant U of a transistor; designing a linear, lossless, reciprocal network embedding the transistor so that the final equivalent S-, Y-, or Z-parameters satisfy the condition: S ? 21 S 12 = Y 2 ? ? 1 Y 1 ? ? 2 = Z 2 ? ? 1 Z 1 ? ? 2 = - [ ( 2 ? U - 1 ) + 2 ? U ? ( U - 1 ) ] ; embedding the transistor into the linear, lossless, reciprocal network; and constructing simultaneous conjugate matching.

Abstract: A computer-aided simulation method for an atomic-resolution scanning Seebeck microscope (SSM) image is provided. In the computer-aided simulation method, a computer may calculate a local thermoelectric voltage for a position of a voltage probe, to acquire an SSM image corresponding to the position.

Abstract: The present invention relates to a hydrogen production module by an integrated reaction/separation process, and a hydrogen production reactor using the same, and more specifically, provides a hydrogen production apparatus which laminates a plurality of layered unit cells, is mounted in a pressure-resistant chamber, and can be operated at a high pressure, wherein the unit cell comprises a first modified catalyst, and a second modified catalyst opposite to a hydrogen separator. The hydrogen production module can produce hydrogen using a hydrocarbon, carbon monoxide and an alcohol as sources. Particularly, all the modified catalysts are formed into a porous metal plate form, thereby maximizing the heat transfer effect necessary for reaction.

Abstract: A power amplifier according to examples includes an amplifying circuit configured to amplify an input signal, a feedback circuit configured to feedback the amplified signal to the amplifying unit, and a feedback controlling circuit configured to control a power of the fed-back signal based on a power of the input signal. The feedback controlling unit performs controlling so that the power of the fed-back signal is increased as the power of the input signal is increased.

Abstract: A power amplifier include an amplifier including at least one field effect transistor (FET) that operates in an amplifying stage configured to amplify an input signal, and a body controller configured to control a bias voltage of a body terminal of the FET based on a power of the input signal. The body controller performs controlling so that the bias voltage of the body terminal is reduced in response to the power of the input signal being increased. Accordingly, such a power amplifier exhibits improved linearity.

Abstract: A semiconductor element includes: a substrate; a gate dielectric layer formed over the substrate; a flat band voltage adjusting layer formed over the gate dielectric layer; and an intermediate layer formed between the gate dielectric layer and the flat band voltage adjusting layer. A negative flat band voltage generated at the intermediate layer and a positive flat band voltage generated between the substrate and the gate dielectric layer may offset each other.

Abstract: A method and apparatus for operating an analog beam is provided. The apparatus includes a hybrid beam-forming structure having a small number of digital chains provided in a digital stage and a signal is transmitted and received in a Time Division Multiple Access (TDMA) scheme. The apparatus includes an analog beam-forming operating unit configured to change the analog beam for a counterpart device for which use of a next frame is to be permitted, upon receiving a request for using the next frame from at least one of multiple devices that transmit and receive signals in units of frames and a communication unit configured to transmit information indicating that the analog beam is changed to permit the use of the next frame by the counterpart device to the multiple devices.

Abstract: A driver for semiconductor memory, comprising: a storage unit configured to match and store a memory cell address and bucket charge current data corresponding to the memory cell address; a selection controller configured to receive the memory cell address and a target charge current data, and output a bucket charge current select signal and a target charge current select signal corresponding to the bucket charge current data and the target charge current data, respectively, by referring to the storage unit; and a current supply unit configured to supply a bucket charge current and a target charge current in response to the bucket charge current select signal and the target charge current select signal, respectively.