Abstract: A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal includes a basic unit having a plurality of series connected delay elements outputs from each delay element are all connected to an AND/NAND gate. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. A succeeding section including plural basic units hones the signal such that jitter elements are removed. By the output of this section time duty cycles are uneven, a positive edge triggered flip-flop is then used to obtain 50% duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.

Abstract: An analogue to digital converter has input for receiving an analogue signal and a frequency modulator for modulating the frequency of a carrier signal in dependence upon the analogue input signal. A digital counter counts the time between successive events in the modulated signal to provide digital signals representative of the analogue input signal.