Abstract: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected to the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).

Abstract: A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the package and a die pad disposed in a central region formed by the plurality of leads. The die pad includes a first die pad surface disposed at the first package face, and a second die pad surface opposite the first die pad surface. The semiconductor device is attached to a central region of the second die pad surface, and a portion of the second die pad surface extending outward from the die is roughened to improve adhesion of the die pad to the molding compound. In other aspects, grooves are disposed in the first and/or second die pad surfaces to further promote adhesion of the die pad and to prevent moisture from permeating into the vicinity of the semiconductor chip.

Abstract: A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture, a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a package strip (10) may consist of a row (linear array) of groups of die attach areas (e.g. in a rectangular array of four). The heat spreader precursor (20) may accommodate one such group or multiple groups along the package strip (10). The package strip (10) may then be singulated to form the individual packages. Each singulated package includes a die (14), its associated substrate 16 (e.g., either a lead frame or interposer type substrate) and a portion of the heat spreader precursor (24) as a heat spreader (20).

Abstract: A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substanial exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) form a cavity (102).

Abstract: A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pads on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled use a lead frame having pre-formed leads, with or without taping, or it can employ the use of partially etched lead frames. A stack of the semiconductor device packages may be formed.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is encapsulated. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is encapsulated. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.