Abstract: A sensor, method, and system for sensing corrosion. The sensor may be used to monitor the integrity of structural elements. The sensor, method, and system utilizing an inductive element formed on the substrate and having a first inductive loop and a second inductive loop. The sensor also includes a sensing element electrically connecting one end of the first inductive loop to an opposing end of the second inductive loop. Prior to dissolution of the sensing element, an inductance of the inductive element comprises a first inductance set by the first predetermined number of turns of the inductor coil having a first resonant frequency. After dissolution of the sensing element, the inductance of the inductive element comprises a second inductance reduced from the first inductance.

Abstract: An electronic package includes an adhesion layer between a first substrate and a second substrate. The adhesion layer is patterned to define openings aligned with through-substrate interconnects and corresponding bond pads. A conductive plane is formed between the first substrate and the second substrate, adjacent to the adhesion layer.

Abstract: A corrosion sensor system includes one or more corrosion sensors embedded in a coating material such as an anti-corrosion coating material. Each corrosion sensor may include a resonator disposed on a dielectric substrate, and has a resonant frequency in a radio frequency (RF) range or an infrared (IR) range, and is configured for interacting with an RF or IR excitation signal to produce an RF or IR measurement signal. The corrosion sensor system may be applied to an object for which corrosion is to be monitored. A corrosion detection system includes a data acquisition system that transmits the excitation signal to the corrosion sensor, and receives the measurement signal from the corrosion sensor for analysis to determine whether corrosion has occurred.

Abstract: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected to the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).

Abstract: A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the package and a die pad disposed in a central region formed by the plurality of leads. The die pad includes a first die pad surface disposed at the first package face, and a second die pad surface opposite the first die pad surface. The semiconductor device is attached to a central region of the second die pad surface, and a portion of the second die pad surface extending outward from the die is roughened to improve adhesion of the die pad to the molding compound. In other aspects, grooves are disposed in the first and/or second die pad surfaces to further promote adhesion of the die pad and to prevent moisture from permeating into the vicinity of the semiconductor chip.

Abstract: A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture, a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a package strip (10) may consist of a row (linear array) of groups of die attach areas (e.g. in a rectangular array of four). The heat spreader precursor (20) may accommodate one such group or multiple groups along the package strip (10). The package strip (10) may then be singulated to form the individual packages. Each singulated package includes a die (14), its associated substrate 16 (e.g., either a lead frame or interposer type substrate) and a portion of the heat spreader precursor (24) as a heat spreader (20).

Abstract: A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substanial exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) form a cavity (102).

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is encapsulated. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is encapsulated. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A method of forming solder bumps on a chip or wafer for flip-chip applications comprises the steps of providing a chip or wafer having a plurality of metal bonds pads which provide electrical connection to the chip or wafer, and applying a solder bump comprising pure tin or a tin alloy selected from tin-copper, tin-silver, tin-bismuth or tin-silver-copper by an electroplating technique, and melting the solder bumps by heating to a temperature above the bump melting point to effect reflow.

Abstract: A semiconductor wafer having solder bumps thereon for use in flip-chip bonded integrated circuits comprises a semiconductor substrate formed with metal bond pads at selected locations thereon, a metal electroplating buss layer or layers over the bond pads, a layer of solder-wettable under bump metal on the buss layer, a layer of barrier metal which overlies and encapsulates the solder-wettable metal, and a solder bump formed on the barrier metal.

Abstract: A method of fabrication of solder bumps on a semiconductor wafer provided with metal bond pads comprises the steps of: (a) applying a metal adhesion/barrier/electroplating buss layer or layers on at least the bond pads; (b) forming a layer of a resist in a predefined pattern defining openings therein over the bond pads; (c) applying a layer of solder-wettable under bump metal into the openings; (d) removing a volume of resist from the regions of the openings to create an opening between an edge of the layer of wettable metal and the resist; (e) applying a layer of a barrier metal over the layer of solder-wettable metal including the openings created at step (d) while encapsulates the layer of wettable metal; (f) fabricating a solder bump onto the layer of barrier metal; and (g) removing the resist material; and (h) removing any exposed adhesion/barrier layer.

Abstract: There is provided an edge connectable electronic package. The package has a metallic base at least partially coated with a dielectric layer. An interconnection means taking the form of either a leadframe or a circuit trace is electrically interconnected to an encased semiconductor device. The opposing end of the interconnection means extends to the package perimeter for interconnection to a socket or brazing to external leads.

Abstract: There is provided a ball grid array package for housing semiconductor devices. The package has a metallic base with conductive vias extending through holes formed in the base. The conductive vias terminate adjacent an exterior surface of the base. A dielectric coating on at least part of the base and through hole walls electrically isolates the metallic base from the package circuitry.

Abstract: A method of making a slotless electric motor wherein the active winding segments are adhesively affixed to a support surface or previously deposited active wire segments to form a self-supporting winding structure. The self-supporting structure is then secured in a magnetic structure of the slotless stator.

Abstract: The bending of a ball grid array electronic package having a metallic base is reduced minimizing stresses applied to the innermost row of solder balls when the package base is cyclically heated and cooled. Reducing the stresses applied to the solder balls increases the number of thermal cycles before solder ball fracture causes device failure. Among the means disclosed to reduce the bending moment are a bimetallic composite base, an integral stiffener, a centrally disposed cover bonded to an external structure and a package base with a stress accommodating depressed portion.

Abstract: A method of making a slotless electric motor wherein the active winding segments are adhesively affixed to a support surface or previously deposited active wire segments to form a self-supporting winding structure. The self-supporting structure is then secured in a magnetic structure of the slotless stator.

Abstract: An optical inspection system for inspecting faults on circuit boards like printed circuit boards and wire scribed circuit boards is disclosed. A video camera for receiving desired images of hole sites on a wire circuit board is provided. The camera converts each image to electrical video signals. A frame grabber converts electrical video signals to a plurality of pixels and stores information representing color element values contained in each of the pixels. A panel feature detector receives the color element values of the pixel that has to be analyzed and provides a wire indication when the color element value of the pixel corresponds to the wire feature. A fault detector circuit receives the wire indication from the panel feature detector corresponding to predetermined pixels associated with the hole site for determining faults on the circuit board.

Abstract: An apparatus and method for wire termination in wire scribed circuit boards is provided. The system includes a plurality of wires having termination areas, scribed on an insulating substrate. The top portion of the termination areas is then removed by a router to expose the wire with a flat surface. The exposed portion of the wire is then covered by a metal suitable for electrical connection bonding.