Abstract: The present invention discloses a wafer which includes a semiconductor substrate having a top surface and a device layer disposed near the top surface for fabrication of integrated circuits (ICs) therein. The wafer also includes an insulating layer beneath the device layer for insulating the device layer with the ICs to be fabricated therein. The wafer further includes a doped region in the substrate. The doped region may be a layer beneath the insulating layer. The doped region is a region of sufficient volume whereby the doped region may be used as a charge sink for protecting the IC devices to be fabricated on the device layer from being damaged by the electric static discharge (ESD) and electric over stress (EOS). Furthermore, the doped region is a region of sufficient dopant concentration whereby the doped region may be used as an electrical connecting means for the IC devices to be fabricated in the device layer such that the doped region becomes a part of integration of the IC devices.