Abstract: The present invention discloses a wafer which includes a semiconductor substrate having a top surface and a device layer disposed near the top surface for fabrication of integrated circuits (ICs) therein. The wafer also includes an insulating layer beneath the device layer for insulating the device layer with the ICs to be fabricated therein. The wafer further includes a doped region in the substrate. The doped region may be a layer beneath the insulating layer. The doped region is a region of sufficient volume whereby the doped region may be used as a charge sink for protecting the IC devices to be fabricated on the device layer from being damaged by the electric static discharge (ESD) and electric over stress (EOS). Furthermore, the doped region is a region of sufficient dopant concentration whereby the doped region may be used as an electrical connecting means for the IC devices to be fabricated in the device layer such that the doped region becomes a part of integration of the IC devices.

Abstract: The present invention discloses a wafer which includes a semiconductor substrate having a top surface and a device layer disposed near the top surface for fabrication of integrated circuits (ICs) therein. The wafer also includes an insulating layer beneath the device layer for insulating the device layer with the ICs to be fabricated therein. The wafer further includes a doped region in the substrate. The doped region may be a layer beneath the insulating layer. The doped region is a region of sufficient volume whereby the doped region may be used as a charge sink for protecting the IC devices to be fabricated on the device layer from being damaged by the electric static discharge (ESD) and electric over stress (EOS). Furthermore, the doped region is a region of sufficient dopant concentration whereby the doped region may be used as an electrical connecting means for the IC devices to be fabricated in the device layer such that the doped region becomes a part of integration of the IC devices.

Abstract: An ion source apparatus is disclosed in this invention. The ion source apparatus includes an anode having an interior space for containing a plasma and an opening into the space. The ion source apparatus further includes a hollow cathode within the space. The ion source apparatus further includes a dopant ion-source composed of compounds comprising element selected from a group of elements consisting of silicon and germanium, the dopant ion-source disposed next to the space. The ion source apparatus further includes a voltage means connected to the anode, the hollow cathode, and the dopant ion source for discharging a plasma into the space for bombarding the dopant ion source for generating a dopant ion compound. The ion source apparatus further includes an ion-beam extracting means for extracting the dopant ion compound through the opening. In an alternate preferred embodiment, the ion source apparatus employs an electron beam device to generate the dopant ion compound.

Abstract: A semiconductor having at least one p-channel transistor (10) with shallow p-type doped source/drain regions (16 and 18) which contain boron implanted into the doped regions (16 and 18) in the form of a compound which consists of boron and an element (or elements) selected from the group which consists of element of substrate (21) and elements which forms a solid solution with the substrate (21). In particular, in the case of silicon substrate, the compound may comprise BSi2, B2Si, B4Si and B6Si. The use of such compounds enables the highly reliable contacts to be formed on the p-doped regions.

Abstract: Three process flows for manufacturing the micro-lens array substrates are disclosed. The process flows consist of two main parts. The first part of the process flows involves fabrication of a master mold. The first two process flows utilize photolithography means to print and dry etch the micro-lens array pattern on the substrate, which is covered by a oxidation or a wet etch stopping layer. The desired surface curvature corresponding to the desired size, shape, and pattern of the micro-lens array is created by either oxidizing the exposed silicon layer (in the first process flow) or to wet-etch the exposed SiO2 by using HF solutions (in the second process flow). The third process flow creates damaged areas by using a focused laser light at first. Then, the damaged areas are preferably etched by solutions, leaving the desired surface curvature.

Abstract: A semiconductor having at least one p-channel transistor (10) with shallow p-type doped source/drain regions (16 and 18) which contain boron implanted into the doped regions (16 and 18) in the form of a compound which consists of boron and an element (or elements) selected from the group which consists of element of substrate (21) and elements which forms a solid solution with the substrate (21). In particular, in the case of silicon substrate, the compound may comprise BSi2, B2Si, B4Si and B6Si. The use of such compounds enables the highly reliable contacts to be formed on the p-doped regions.

Abstract: This invention discloses a programmable read-only-memory (PROM). The PROM is formed and supported on a substrate. The PROM includes a transistor region in the substrate including a source region, a drain region and a floating gate region disposed between the drain region and the source region. The PROM further includes a floating gate formed on top of the floating gate region with a single poly layer on the substrate. The PROM further includes a floating gate extension region disposed near the transistor region, the floating gate extension region is connected with the floating gate region. The PROM further includes a control gate formed on the substrate near the floating gate extension region opposite the transistor region whereby a charge state of the floating gate extension region is controlled by the control gate.