Abstract: A cache including a tag storage which compares a portion of the tag address (a "mini-tag") to a respective portion of a request address is provided. If the mini-tag matches, then the way associated with the tag having a match is the way selected for conveying data bytes to the output of the cache. The mini-tag comparison is performed on a field of address bits different from the index field, and the comparison is performed in parallel with the index field decode. The way selection is qualified with the index field decode such that one set and one way of the set is selected for conveying bytes from the cache. The access time of the present cache structure is substantially similar to a direct-mapped cache. However, the present cache strucuture is a set-associative structure. The hit rate and thrashing insensitivity of a set-associative cache are maintained by the present cache.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.