Abstract: An exemplary apparatus for interfacing dies that use incompatible protocols includes a first die that uses a first protocol, a second die that uses a second protocol, and a die management unit communicatively coupled to both the first die and the second die in an integrated circuit. In some examples, the die management unit is configured to translate at least one message between the first protocol and the second protocol to support communication between the first die and the second die. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Shared last level cache usage management for multiple clients is described. In one or more implementations, a system includes a shared last level cache coupled to multiple clients and a dynamic random access memory. The system further includes a linear dropout regulator that supplies power to the shared last level cache. A data fabric included in the system is configured to control a level of the power supplied from the linear dropout regulator to be either a first level or a second level based on usage of the shared last level cache.

Abstract: Systems, apparatuses, and methods for implementing cache line re-reference interval prediction using a physical page address are disclosed. When a cache line is accessed, a controller retrieves a re-reference interval counter value associated with the line. If the counter is less than a first threshold, then the address of the cache line is stored in a small re-use page buffer. If the counter is greater than a second threshold, then the address is stored in a large re-use page buffer. When a new cache line is inserted in the cache, if its address is stored in the small re-use page buffer, then the controller assigns a high priority to the line to cause it to remain in the cache to be re-used. If a match is found in the large re-use page buffer, then the controller assigns a low priority to the line to bias it towards eviction.

Abstract: Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

Abstract: In accordance with the described techniques, a device includes a memory system and a processor communicatively coupled to the memory system. The processor receives a load instruction from the memory system instructing the processor to load data associated with an address. In response, the processor performs a lookup for the address in a bloom filter that tracks zero value cache lines that have previously been accessed. Based on the lookup indicating that a hash of the address is present in the bloom filter, the processor generates zero value data. Furthermore, the processor processes one or more dependent instructions using the zero value data.

Abstract: The disclosed voltage regulator circuit includes an NMOS as the main power device that is coupled to a regulated voltage output. A sensing circuit senses the regulated voltage output, and a reference voltage circuit supplies a correct bias to the flipped-source follower, which amplifies the sensed voltage output. A voltage inversion circuit such as a current mirror provides an inverting gain stage for the sensed voltage output, for driving the NMOS. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A thermal management system for an integrated circuit can include plural micro vapor chambers each configured to operate within their local environment. An exemplary system includes a semiconductor die, a first micro vapor chamber coupled with a first region of the semiconductor die, and a second micro vapor chamber coupled with a second region of the semiconductor die.

Abstract: An integrated circuit die includes a set of electronic circuits disposed on a semiconductor material. The integrated circuit die also includes one or more through-silicon vias that vertically span the semiconductor material to transmit data signals. Additionally, the integrated circuit die includes a programmable delay element integrated with the set of electronic circuits on the semiconductor material and configured to delay data signals. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A disclosed method for consolidating eligible vector instructions can include detecting a plurality of vector instructions within a queue of an integrated circuit. The method can also include consolidating the plurality of vector instructions into a single vector instruction based at least in part on the plurality of instructions satisfying one or more criteria. The method can further include forwarding the single vector instruction through a pipeline of the integrated circuit. Various other devices, systems, and methods are also disclosed.

Abstract: A method includes forming a plurality of thermal sensing elements at predetermined locations on a semiconductor chip proximate to a target location, measuring a temperature of the semiconductor chip at each predetermined location using a corresponding one of the plurality of thermal sensing elements, and determining a temperature at the target location using the temperatures measured at each of the predetermined locations.

Abstract: A technique includes determining a base decision rate; monitoring for key events; and based on the base decision rate and the monitoring, determining a time at which to generate an action to be performed by an application entity of an application. The base decision rate includes a baseline rate at which the application is directed to determine new actions to be performed by the application entity. In some examples, the base decision rate is determined using a trained AI model, by applying information about the state of the application to the model and obtaining the base decision rate in response. In some examples, key events are unexpected events that occur in the application. In some examples, since the base decision rate represents a rate at which to generate actions, given the current state of the application, the key events, which represent unexpected events, override or modify the base decision rate.

Abstract: A technique is provided. The technique includes opening an aperture for processing partial results; receiving partial results in the aperture; and processing the partial results to generate final results.

Abstract: A system-on-chip structure includes a substrate, first and second die disposed over a surface of the substrate and separated by an inter-die gap, a protection layer disposed over a sidewall of each of the first and second die, and a gap fill layer disposed over the protection layers and substantially filling the inter-die gap.

Abstract: Methods of fabricating a semiconductor device include securing a first die to a second die. The first die includes a first clock signal path from a clock source to a first load and passing through a tap point electrically connected to a clock output. The second die includes a second clock signal path from a clock input to a second load. The methods also include connecting the clock input of the second die to the clock output of the first die. A first divergence between the tap point and the first load is substantially the same as a second divergence from the tap point through the clock input and the clock output to the second load. Various other methods, devices, and systems are also disclosed.

Abstract: Devices, methods, and systems for load fusion. In an explicit approach, a first load operation and a second load operation, in a stream of operations, are replaced with a single load operation. One or more operations, configured to move and shift a value stored in a destination register of the single load operation, are inserted after the single load operation in the stream of operations. In an implicit approach, Information of a first load operation is inserted into a tracking table. Information of a second load operation is inserted into the tracking table responsive to an address of the second load operation being within a range. A load operation is executed from an address indicated by the first load operation and from an address indicated by the second load operation based on the tracking table.

Abstract: The disclosed device includes various components; and a control circuit for managing performance states of the components. The control circuit can receive an event trigger corresponding to one of the components, monitor an activity metric for the component, and update a performance state of the component based on the event trigger and the activity metric. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique for improving performance of a hash operation on a processor is provided, in which an input value is hashed into a second value corresponding to a number of bins. The number of bins is an integer that corresponds to a product of first and second integers, the first integer corresponding to a prime number and the second integer corresponding to a power of two. A first modulo hashing operation is performed in which the input value is hashed into the first integer. A second hashing operation is performed using less than all bits of the input value. An output value is formed by concatenating a result of the first hashing operation with a result of the second hashing operation.

Abstract: The disclosed computer-implemented method includes configuring a cache with a cache addressing scheme that increases a capacity of each entry of the cache, compressing a data segment for storing in the cache, and storing metadata of the compression in the cache with the compressed data segment. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data processing system includes a data processor and a memory. The data processor is for issuing memory commands including a first memory command that accesses data of a first size. The memory is operative to transfer data of the first size by separating a first portion of data from a second portion of data by a data gap. The data processor is operable to selectively prioritize and issue a second memory command after issuing the first memory command at a time that fills the data gap.

Abstract: In accordance with the described techniques, a device includes a memory system and a processor communicatively coupled to the memory system. The processor receives a load instruction from the memory system instructing the processor to load data associated with an address. In response, the processor performs a lookup for the address in a bloom filter that tracks zero value cache lines that have previously been accessed. Based on the lookup indicating that a hash of the address is present in the bloom filter, the processor generates zero value data. Furthermore, the processor processes one or more dependent instructions using the zero value data.