Abstract: An integrated circuit device can include a number of test structures, whereby each test structure includes a TSV and a plurality of devices-under-test (DUTs). Each of the DUTs in a test structure has a different positional relationship, such as proximity or orientation, to the TSV. A test system can measure selected parameters such as transistor threshold voltage, leakage current, or other parameters, for each of the DUTs in the test structure. The measurements for different test structures can be combined to characterize nominal values of the measured parameter and its statistical distribution. This information provides an indication of how the measured parameter varies according to the positional relationship of a TSV to a DUT.

Abstract: A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

Abstract: A method and apparatus to improve motion prediction in video processing systems is introduced. When a motion prediction cache completes requesting data for a current macroblock and enters an into idle state, data comprising one or more reference frames is speculatively requested, with the hope that the requested data are will be needed in a subsequent macroblock. If the speculative data is needed, then it is consumed. However, if the speculative data is not needed, then the correct data must be requested and a price is paid for an extra memory read bandwidth. In case the speculative data is the correct data for the subsequent macroblock, the effective memory read latency is reduced and the decode performance increases. The video decoder becomes more immune to memory read latency.

Abstract: Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask.

Abstract: Disclosed herein are a processing unit and a multi-processing unit system that implement a cache-coherency method. Such a multi-processing unit system includes a main memory, a first processing unit, and a second processing unit. The first processing unit and the second processing unit are coupled to the main memory. The first processing unit includes a cache and logic. The cache is configured to store data from the main memory. The logic is configured to maintain an entry in a directory of the cache. The entry indicates whether either of the first processing unit and the second processing unit accesses a data object of a cache line for which the first processing unit is a home node.

Abstract: A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Abstract: One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units.

Abstract: A computer system is provided for compiling program code and a method for compiling program code by a processor. The method, for example, includes, but is not limited to, receiving, by the processor, the program code and compiling, by the processor, the program code, wherein the processor, when compiling the program code, parses the program code and assigns a default address space qualifier to each member functions without a defined address space qualifier and, when the member function is used, infers an address space for each default address qualifier based upon how the respective member function is being used.

Abstract: A method and apparatus for using multiple data rate (MDR) wiring with encoding is described herein. Single data rate wires are replaced with MDR wires and signals are processed through MDR circuitry. The MDR circuitry may include MDR driver circuitry, MDR repeater circuitry and MDR receiver/decoder circuitry. An encoding circuit may be included in the MDR circuitry to mitigate power consumption due to signal toggling rates. The MDR circuitry may be implemented at multiple clock rates, and with source synchronous bus circuitry and clock gates.

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: Methods and apparatuses are provided for power control in a processor. The apparatus comprises a plurality of operational units arranged as a group of operational units. A power consumption monitor determines when cumulative power consumption of the group of operational units exceeds a threshold (e.g., either or both of the cumulative power threshold and the cumulative power rate threshold) during a time interval, after which a filter for issuing instructions to the group of operational units suspends instruction issuance to the group of operational units for the remainder of the time interval. The method comprises monitoring cumulative power consumption by a group of operational units within a processor over a time interval. If the cumulative power consumption of the group of operational units exceeds the threshold, instruction issuance to the group of operational units is suspended for the remainder of the time interval.

Abstract: Power gating control and related circuitry for integrated circuits is described herein. A centralized power gating control circuit uses trigger circuits to control the on/off switching of power gating circuits distributed at different points in a chip, integrated circuit, module or block (collectively “IC”). The power gating circuits may include power gates partitioned for sleep and shutdown modes. The shutdown mode power gates may employ multi-level power gate architecture to minimize inrush current during power-up of the IC. Each level may be associated with or tied to a trigger circuit and activated based on a voltage level reaching the voltage threshold of the trigger circuit. The power gating control and related circuitry may be embedded in the IC.

Abstract: A shared memory controller and method of operation are provided. The shared memory controller is configured for use with a plurality of processors such as a central processing unit or a graphics processing unit. The shared memory controller includes a command queue configured to hold a plurality of memory commands from the plurality of processors, each memory command having associated priority information. The shared memory controller includes boost logic configured to identify a latency sensitive memory command and update the priority information associated with the memory command to identify the memory command as latency sensitive. The boost logic may be configured to identify a latency sensitive processor command. The boost logic may be configured to track time duration between successive latency sensitive memory commands.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract: Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

Abstract: A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on sampled signals within one or more functional blocks in the processor, rather than based on temperature. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent. Responsive to receiving and processing the average power consumption number, the external agent may cause changes in a cooling system.

Abstract: A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.

Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Abstract: A system includes multiple TAP controllers that can be independently powered up and down. When a first TAP controller is powered up from a powered-down state while a second TAP controller is already in a powered-up state, the first TAP controller is reset causing the first TAP controller to enter a reset state in response to the power-up of a module on which the first TAP controller is disposed. The first TAP controller enters an idle state and its control signal is gated to hold the first TAP controller in the idle state until the second TAP controller enters the idle state. Subsequently, the first TAP controller is released such that the control signal supplied to the first and second TAP controllers are equal, thereby synchronizing the first TAP controller and the second TAP controller.

Abstract: A method and apparatus for processing multi-cycle instructions include picking a multi-cycle instruction and directing the picked multi-cycle instruction to a pipeline. The pipeline includes a pipeline control configured to detect a latency and a repeat rate of the picked multi-cycle instruction and to count clock cycles based on the detected latency and the detected repeat rate. The method and apparatus further include detecting the repeat rate and the latency of the picked multi-cycle instruction, and counting clock cycles based on the detected repeat rate and the latency of the picked multi-cycle instruction.