Abstract: The disclosed device includes a first register that stores a cumulative delta value and a second register that stores an average cache hit rate. The device also includes a control circuit that calculates a cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. The control circuit also updates the average cache hit rate based on the updated cumulative delta value, and can update a cache allocation policy based on the updated average cache hit rate. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique for rendering is provided. The technique includes determining a first correspondence between a screen space and a shade space in a visibility pass; selecting a size for a shade space tile based on the correspondence between the screen space and the shade space; and shading the shade space tile based on the material texture correspondence.

Abstract: The disclosed device includes multiple data elements each configured to send a bit of a bit sequence by toggling at most half of a number of bits from a previously sent bit sequence. The bit sequence can first be biased and then XORed with the previously sent bit sequence. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A semiconductor electrostatic discharge (ESD) protection circuit comprises an N diode for limiting negative going voltages with reference to ground (VSS) and a P diode for limiting positive going voltages with reference to a positive supply voltage (VDD). The N-diode is formed in a single P-well surrounded by an N-well ring. The P-diode is formed in a single N-well surrounded by a P-well ring. The N-diode comprises a plurality of N+ fingers, each N+ finger is surrounded by a P+ guard ring. The P-diode comprises a plurality of P+ fingers, each P+ finger surrounded by an N+ guard ring. The plurality of N+ fingers and P+ fingers are coupled to an input-output pad. The P+ guard rings are coupled to ground (VSS) and the N+ guard rings are coupled to the positive supply voltage (VDD).

Abstract: The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique for rendering is provided. The technique includes generating a first gradient for a shade space texture tile, wherein the first gradient reflects a relationship between shade space texel spacing and screen space pixel spacing; generating a second gradient for a shade space texel of the shade space texture tile, wherein the second gradient reflects a relationship between material texel spacing and shade space texel spacing; combining the first gradient and the second gradient to obtain a third gradient; and performing anisotropic filtering on the material texture using the third gradient to obtain a value for the shade space texel.

Abstract: Selecting intermediate representation transformation for compilations is described. In accordance with the described techniques, source code is received to be compiled by a compilation system for execution by a processor of hardware. Intermediate representation transformations are selected for the source code based on system load information associated with the hardware. The intermediate representation transformations are output to the compilation system.

Abstract: Scheduling requests of multiple processing-in-memory threads and requests of multiple non-processing-in-memory threads is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory threads and a plurality of non-processing-in-memory threads from a host. The memory controller schedules an order of execution for requests of the plurality of processing-in-memory threads and requests of the plurality of non-processing-in-memory threads based on a priority associated with each of the requests and a current operating mode of the system. Requests are maintained in queues at the memory controller and are individually assigned a priority level based on time enqueued at the memory controller. Requests of a different mode than a current operating mode of the system are delayed for scheduling until at least one different mode request is escalated to a maximum priority value, at which point the memory controller initiates a system mode switch.

Abstract: A technique for texture filtering. A transition is made from a first mipmap corresponding to a first texture resolution to a second mipmap corresponding to a second texture resolution. The first texture resolution is lower than the second texture resolution. As compared to standard trilinear filtering, initiation of the transition is delayed by an offset (or bias), which serves to delay the initial use of the second mipmap until it has been loaded. Following initiation of the transition, first and second weightings are selected with a nonlinear filter, and the system interpolates between the first mipmap and the second mipmap by applying the weightings. During an initial portion of the transition, the nonlinear filter has a slope that is higher than that of the standard trilinear filter.

Abstract: A method for server level cooling can include providing a printed circuit board and attaching a cooling system to the printed circuit board. The cooling system can be configured for placement thereon of two or more expansion cards having back side power delivery components. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device includes memory channel interfaces and mesh lanes each corresponding to a particular memory channel interface. The device also includes ports and various routing elements interconnecting the ports, mesh lanes, memory channel interfaces. The device further includes a control circuit configured to receive a data packet on a port, select a mesh lane based on a destination of the data packet, and forward the data packet to the selected mesh lane via a routing element. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. Once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.

Abstract: A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An electronic device includes a non-volatile memory and a memory controller. The memory controller selects, from the type-duration table, a duration for which data of a type of data is to be stored in a non-volatile memory. The memory controller writes the data to the non-volatile memory using values of one or more write parameters selected by the memory controller based on the duration. The memory controller sets an expected lifetime value in a record for the data in the expected lifetime table to indicate an expected lifetime of the data in the non-volatile memory.

Abstract: An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.

Abstract: A disclosed method for restoring bus functionality includes detecting, by an automatic bus recovery block, that at least one target device on a bus pulls at least one line of the bus to a low level. The method also includes initiating, by the automatic bus recovery block, a timer to time a duration of the low level of the line. Additionally, the method includes detecting, by the automatic bus recovery block, that the duration of the low level of the line exceeds a predetermined time limit. Furthermore, the method includes alerting, by the automatic bus recovery block, a controller device on the bus that the duration of the low level exceeds the predetermined time limit to reset the line of the bus to a high level. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.

Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.

Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.