Abstract: Speculative execution using a page-level tracked load order queue includes: determining that a first load instruction targets a determined memory region; and in response to the first load instruction targeting the determined memory region, adding an entry to a page-level tracked load order queue instead of a load order queue, where the entry indicates a page address of a target of the first load instruction.

Abstract: The disclosed computer-implemented method for multi-tier multi-die modules may include bonding a front side of a first plurality of dies to a first carrier, forming a first wafer; preparing a back-side surface of the first wafer for hybrid bonding; bonding a back side of a second plurality of dies to a second carrier, forming a second wafer; preparing a front-side surface of the second wafer for hybrid bonding; and hybrid bonding the first wafer with the second wafer. Various other methods, apparatuses, and systems are also disclosed.

Abstract: A processor includes an accelerated access circuit, a data structure, and a hardware scheduler. The data structure is managed by software and bound to the accelerated access circuit. The hardware scheduler is configured to schedule, on the accelerated access circuit, a work item requesting access to the data structure. The accelerated access circuit is configured to receive a request from the work item to access the data structure. Responsive to the request, the accelerated access circuit is further configured to serialize access by the work item to the data structure thereby preventing other work items from accessing the data structure.

Abstract: A rack is provided. In one aspect, a rack includes a plurality of trays mounted in the rack in a first orientation. The rack also includes a cable cartridge mounted in the rack in a second orientation perpendicular to the first orientation. The cable cartridge includes (i) connectors configured to connect to tray connectors on respective sides of the plurality of trays and (ii) cables connected to the connectors in the cable cartridge to facilitate communication between the plurality of trays.

Abstract: A driving power stage can receive a PWM signal from the PWM controller and output a PWM signal to a secondary power stage. The secondary power stage can be turned off by the driving power stage during a light-load mode. For a single-phase application, the driving power stage can turn off a switch, causing the power stage to work as a regular power stage. Various other methods and systems are also disclosed.

Abstract: The disclosed device includes a device comprising a device-attached memory and a trust controller for confidential computing. The trust controller can maintain a record of devices that are permitted to access the device-attached memory, receive updates to the record, and verify, based on the record, attempts to access the memory.

Abstract: Offloading quantization of directional blocked data formats to near-memory units is described. In one or more implementations, a system includes a processing-in-memory memory circuit configured to store data. The system can also include a memory controller circuit configured to map the data to the processing-in-memory memory circuit. The system can also include a processing-in-memory arithmetic logic unit configured to quantize the data from a scalar format to a directional blocked data format. The scalar format can be or can include a scalar format such as BFloat 16. The directional blocked data format can be or can include a microscaling format.

Abstract: An electronic device includes a memory and controller circuitry. The controller circuitry, responsive to a read request to read encrypted data stored in the memory, acquires, from metadata stored with the encrypted data in the memory, an ownership identifier identifying a type of writing entity that stored the encrypted data in the memory. The controller circuitry uses the ownership identifier to control whether, when responding to the read request, data decrypted from the encrypted data is returned or substitute data is returned instead of data decrypted from the encrypted data.

Abstract: Disclosed herein are a package substrate, a chip package, and method for fabricating the same. The package substrate includes a package core comprising vias; a plurality of build-up layers disposed on an upper surface of the package core, the plurality of build-up layers comprising metal traces connected with the vias; and a magnetic core inductor disposed in a cavity of the package core. The magnetic core inductor includes a magnetic inlay, and a first metal layer disposed in the cavity on the magnetic inlay below the plurality of build-up layers. A second metal layer may be further disposed between the first metal layer and the metal traces. Both the first and second metal layers may be floating or grounded. The first and second metal layers are configured to shield other electronic components from being interfered by the magnetic field generated by the magnetic core inductor.

Abstract: A computing device and a method of performing crash analysis is provided. Each compute unit of an accelerated processor is configured to execute an application in a crash analysis operation mode, different from a normal operation mode, by executing a single instruction in isolation from any other instruction such that execution of the single instruction is completed prior to beginning execution of any of the other instructions. Examples of selectable crash analysis operation modes include a first mode in which execution of each memory instruction is completed prior to beginning execution of a next instruction, a second mode in which execution of each ALU instruction is completed prior to beginning execution of a next instruction, and a third mode in which execution of both memory and ALU instructions are completed prior to beginning execution of a next instruction.

Abstract: An integrated circuit device performs a method for adjusting a clock signal frequency. The method includes receiving a workload, and determining a latency parameter by sampling data of the workload. Further, an activation parameter is determined based on a data bandwidth on the workload. A clock signal of the IC device is adjusted based on the latency parameter and the activation parameter.

Abstract: Embodiments herein describe active condensation management for a sub-ambient cooling device. In an example, the sub-ambient cooling device includes first and second TEC systems arranged in a stacked configuration, where the first TEC system is positioned between an integrated circuit device and the second TEC system, an IC-facing surface of the second TEC system has features (e.g., channels and ribs) that control a location at which condensation occurs and that direct the condensation to a catch basin positioned within a gap between the TEC systems. The features may be designed to function in multiple orientations, which may be useful to permit a cooled device to operate upright or on its side. The sub-ambient cooling device may include an enclosure to define/restrict a volume of space to be dehumidified.

Abstract: A three-dimensional semiconductor package assembly includes a die. The die includes a plurality of through silicon vias (TSVs). The TSVs includes a first TSV and a second TSV. The first TSV supplies power from an active surface of the die to a back surface of the die. The assembly also includes a passive device coupled to the back surface of the die such that conductive contacts of the passive device electrically interface with the TSVs. The first passive device receives power through the first TSV and supplies power to the first die through the second TSV.

Abstract: Implementing a circuit design for a target integrated circuit includes receiving guide information including placement information for a circuit design from a prior implementation flow. A light incremental flow is performed on the circuit design using the guide information. The light incremental flow generates a placed and routed circuit design that re-uses at least a portion of the placement information from the prior implementation flow.

Abstract: A process of making a stacked semiconductor die can include a step of forming a conformal film of insulating material on one or more surfaces of a singulated semiconductor die. In some examples, the presence of the film tends to reduce the formation of cracks during the die stacking process.

Abstract: A computing system includes a communication system comprising a glitch filter circuitry disposed in an integrated circuit (IC) device configured to receive an input signal and provide a glitch filter output signal based on the input signal. The glitch filter circuitry includes a control path circuitry configured to receive the input signal and generate a control signal based on detecting a glitch within the input signal, the control path circuitry including a configurable resistor capacitor (RC) filter circuitry configured to deliver a configurable RC filter circuitry output signal based on one or more selection signals. The control signal is based on the configurable RC filter circuitry output signal, and a data path circuitry configured to receive the control signal and mitigate glitches within the input signal based on the control signal.

Abstract: An alignment system is provided. In one aspect, the alignment system includes a tray configured to mount into a rack. The tray includes a first electrical connector and a first alignment element. The alignment system also includes a component configured to mount into the rack. The component includes a second electrical connector and a second alignment element. The first alignment element is configured to mate with the second alignment element when the tray is slid into the rack. Mating of the first and second alignment elements aligns the first and second electrical connectors. The first and second electrical connectors are disposed along respective axes that are parallel with a direction that the tray is slid into the rack.

Abstract: A request is received from an application to present content generated by the application in an overlay plane of a multi-plane display system. Responsive to determining that current system resources support presentation of the generated content in the overlay plane, frames of the generated content are displayed in the overlay plane and captured directly from the overlay plane such that the captured frames may be provided to one or more remote client computing systems independently of frames captured from one or more additional overlay planes and from an underlying composited desktop layer. Identifiers of prioritized applications may be maintained based on user preferences to determine specific applications for which generated content is enabled for display via overlay plane.

Abstract: Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at least one register configured to store a ranking for each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of the respective portion of the memory. A memory controller is configured to dynamically refresh the portions of the memory at different times based on the ranking for each of the plurality of portions of the memory stored in the at least one register.

Abstract: Systems and techniques for efficient memory setting are described. Memory setting is a common operation used by computing systems (e.g., operating systems and hypervisors) to write specific values, such as all ones or all zeroes, to obscure the current memory values to a memory region. In one example, a processor core issues a data-less write request that identifies a target address range for setting to a set value (e.g., ones, zeroes, or a random combination thereof). The data-less write request generally does not include a data payload. Instead, the set value is determined based on an index value associated with a lookup table at the memory controller or memory system or based on the target address range. In this way, the described systems and techniques accelerate memory setting operations with minimal data movement to save energy.