Abstract: A system includes memory hardware including a memory and a processing-in-memory (PIM) component. A system includes a host including at least one core. The PIM component includes a memory die (e.g., a dynamic random access memory (DRAM) die) and a base die, e.g., a logic die. The base die includes one or more PIM arithmetic logic units (ALU) and one or more sense amplifiers. In at least some implementations the base die includes a shared static random-access memory (SRAM) cache that is shared between different ALU that reside in the base die.

Abstract: Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

Abstract: An apparatus and method for efficiently creating less computationally intensive nodes for a neural network. In various implementations, a computing system includes a memory that stores multiple input data values for training a neural network, and a processor. Rather than determine a bit width P of an integer accumulator of a node of the neural network based on bit widths of the input data values and corresponding weight values, the processor selects the bit width P during training. The processor adjusts the magnitudes of the weight values during iterative stages of training the node such that an L1 norm value of the weight values of the node does not exceed a corresponding weight magnitude limit.

Abstract: The disclosed device for high-voltage-tolerant level shifters can include a level shifter device configured to shift an input signal from an input voltage range to an output voltage range, where a span from a bottom of the input voltage range to a top of the output voltage range is greater than a voltage differential tolerance of any of the plurality of transistors. Various other devices and systems are also disclosed.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, in a first iteration of a ray traversal technique, traversing to an instance node of a bounding volume hierarchy; in a second iteration of the ray traversal technique that is subsequent to the first iteration, transforming a ray based on an instance transform of the instance node to generate a transformed ray; and in the second iteration, performing a ray-box intersection test for box node data of the instance node based on the transformed ray.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, submitting a plurality of intersection test requests to an intersection test unit, wherein the plurality of intersection test requests are submitted prior to receiving results of any of the intersection test requests from the intersection test unit.

Abstract: A processing unit (PU) is configured to generate reference values based on previously displayed frames in order to decode encoded frames having one or more noise-based effects. To this end, the PU includes a noise effect circuitry configured to determine noise values associated with a previously displayed frame. The noise effect circuitry then subtracts respective noise values from the pixel values of the previously displayed frame to determine reference values for decoding an encoded frame. Further, the PU includes a decoder that decodes the encoded frame based on the determined reference values.

Abstract: A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.

Abstract: Selecting intermediate representation transformation for compilations is described. In accordance with the described techniques, source code is received to be compiled by a compilation system for execution by a processor of hardware. Intermediate representation transformations are selected for the source code based on system load information associated with the hardware. The intermediate representation transformations are output to the compilation system.

Abstract: A processor configured to execute one or more virtual machines (VMs) includes an input-output memory management unit (IOMMU) configured to handle memory-mapped input-output (MMIO) requests and direct memory access (DMA) requests from a processor core of the processor or one or more input/output (I/O) devices. In response to receiving an MMIO or DMA request, the IOMMU is configured to determine a VM associated with the request. The IOMMU then checks a security indicator field of an address space identifier (ASID) mask table to determine if the VM was previously the target of an attack by a malicious entity. In response to the VM previously being a target of an attack, the IOMMU denies the received MMIO or DMA request.

Abstract: Speculative cache invalidation techniques for processing-in-memory instructions are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a processing-in-memory request is valid in memory. The system employs speculative evaluation logic to identify whether the data associated with the processing-in-memory request is stored in the cache system before the processing-in-memory request is transmitted to the cache coherence controller. If the data is stored in the cache system, the cache system locally invalidates or flushes the data to avoid stalling the processing-in-memory request during a cache directory lookup.

Abstract: Devices, methods and systems for managing resources in a computing device. Information regarding resource usage is captured. A prediction is generated, based on the information, that resource usage by a processor will exceed a threshold during an upcoming time. An operating parameter of the processor is adjusted, based on the prediction. In some implementations, information regarding memory bandwidth is captured. A prediction is generated, based on the information, that a memory region stored in a first memory device will be addressed by a memory intensive instruction during an upcoming time period. Data stored in the memory region is moved to a second memory device, based on the prediction.

Abstract: A substrate includes a location for coupling one or more chiplets to the substrate. The location has dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the location. Additionally, the location includes an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region that includes a power interface having connections for the one or more chiplets.

Abstract: An imaging system improves image quality, such as during a videoconference, by adjusting one or more captured images based on a model of a scene, a conference participant's face or a combination thereof. The images are adjusted in response to identification of relatively poor ambient conditions for image capture. The imaging system, such as a videoconference system, is thus able to display relatively high-quality images even in relatively poor conditions for image capture.

Abstract: A processing system includes a memory configured to store encrypted information representing state and control information for a guest virtual machine. The processing system further includes a processor configured to selectively reserve exclusive use of a set of performance monitoring counters by the guest virtual machine during execution of the guest virtual machine based on a state of a first control field accessed from the encrypted information for the guest virtual machine. The processor further is configured to permit or deny use of the set of performance monitoring counters by the guest virtual machine based on a state of a second control field set by a hypervisor and accessed from the decryption of the encrypted information for the guest virtual machine accessed from the memory.

Abstract: A system and method for characterizing the data used to train a model for machine learning inference. Training data and production data may both be fingerprinted, and the fingerprints may be compared to detect undesirable variances between training and production data. This may allow performance issues relating to differences in the training data set versus the production data set to be more easily identified. Parameters used for characterization can be determined based on the type of training data such as numerical data, image data, or audio data.

Abstract: Systems and methods for correlating performance on bare metal systems with virtualized instances such as those commonly used in cloud computing systems are disclosed. Performance data may be collected from different bare metal and cloud instances. The performance data may be used to predict the performance of an application on another system, even if the particular performance counter of interest is unavailable on the system. Using measured and estimated performance counters (e.g., instructions counters), multiple measured and unmeasured but predicted instances can be compared and sorted to assist the user in making an informed decision when selecting where to run their instance and what configuration to use.

Abstract: Disclosed devices, systems, and methods may enhance communication protocols for low latency applications. Systems may include a device and a host interconnected by a high-performance interconnect and/or communication link. The device may comprise a transmitter, a receiver, and a control unit that may manage a credit-based flow control mechanism. In some aspects, the device may initiate a push write request, send a data header with an identifier (UQID) matching the push write request identifier (CQID), and transmit the data payload. The host may receive the push write request, match the UQID with the CQID, perform the write operation, and send a completion message back to the device. The method may involve ensuring sufficient credits before initiating the push write transaction, which may help prevent data loss and ensure reliable delivery. The push write mechanism may reduce the number of link traversals required for device-to-host memory writes, potentially lowering overall latency.

Abstract: A hardware-accelerated siamese neural network device includes a first hardware-accelerated convolutional neural network (CNN) circuit configured to apply a certain weight to a first input at a specific moment of an operation. The hardware-accelerated siamese neural network device also includes a second hardware-accelerated CNN circuit configured to apply the certain weight to a second input at the specific moment of the operation. In addition, the hardware-accelerated siamese neural network device includes a classifier circuit configured to generate a score that represents a degree of similarity between the first input and the second input. Various other devices, systems, and methods are also disclosed.