Abstract: A distributed processing system includes one or more accelerated units (AUs) connected to a network. To control access to the AUs by one or more users over the network, the distributed processing system includes a control plane circuitry connected to the network. The control plane circuitry is configured to grant a user access to one or more AUs connected to the network based on user security data stored at the control plane circuitry. The security data stored at the control plane circuitry indicates which resources of one or more AUs connected to the network one or more users are authorized to access.

Abstract: A processor includes two or more core dies each including one or more processor cores and/or associated with one or more input/output dies. A hypervisor, firmware in a central processing unit (CPU), or software or firmware located outside of the CPU assigns virtual machines or threads to a first core die and disconnects power from a second core die with no active threads or cores, e.g., by adjusting one or more voltage regulators associated with the second core die, while still providing power to the first core die. In some implementations, active threads or processing cores are migrated from sparsely allocated processing cores or core dies into a reduced number of core dies. Power usage is minimized by disconnecting one or more inactive core dies from power while performance is maximized by increasing the clock frequency of remaining active core dies or remaining active processing cores located therein.

Abstract: The disclosed method includes waveform extractions from a cross-talking environment by measuring a signal from a target circuit/transistor while deterministically stimulating a second circuit using a second laser and post-processing. The method includes analyzing the measured signal detecting a fault or an error in one of the circuits based on the analysis. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: In some implementations, the device may include detecting a speculative load hardening indicator in a first block of code. In addition, the device may include selectively suppressing hardware speculative execution for instructions in the first block of code associated with the detected speculative load hardening indicator.

Abstract: Techniques for performing machine learning operations are provided. The techniques include configuring a first portion of a first chiplet as a cache; performing caching operations via the first portion; configuring at least a first sub-portion of the first portion of the chiplet as directly-accessible memory; and performing machine learning operations with the first sub-portion by a machine learning accelerator within the first chiplet.

Abstract: Systems, methods, and devices for determining a derived counter value based on a hardware performance counter. Example devices include input circuitry configured to input a hardware performance counter value; counter engine circuitry configured to determine the derived counter value by applying a model to the hardware performance counter value; and output circuitry configured to communicate the derived counter value to a consumer. In some examples, the consumer includes an operating system scheduler, a memory controller, a power manager, or a data prefetcher, or a cache controller. In some examples, the processor includes circuitry configured to dynamically change the model during operation of the processor. In some examples, the model includes or is generated by an artificial neural network (ANN).

Abstract: A processing unit manages temperature by correlating readings from a plurality of external temperature sensors to a skin temperature of the processing unit, wherein the correlation is based on characteristics of a computer chassis that is to include the processing unit. The processing unit is mounted on a printed circuit board (PCB) or other substrate that is to be placed in a computer chassis. Each of a plurality of temperature sensors is placed at a different location of the PCB to provide temperature readings from a variety of locations of the PCB. A temperature controller of the processing unit receives temperature readings from the plurality of sensors and correlates the temperature readings with a skin temperature of the processing unit based on a plurality of correlation values.

Abstract: A processing system includes one or more network-attached hostless accelerator (NAHA) units each having an integrated circuit. The integrated circuit of each NAHA unit includes a memory and a first network interface controller configured to communicatively couple the memory to a network such that the memory of the NAHA unit is communicatively coupled to one or more memories of other NAHA units via the network. Additionally, a NAHA unit of the processing system includes one or more processor cores configured to execute an instruction to generate a result. Further, the one or more processor cores of the NAHA unit are configured to store the result in the one or more memories of the other NAHA units.

Abstract: A data processor includes a memory accessing agent for generating memory access requests for a memory that includes a plurality of banks, and a memory controller. The memory controller includes a command queue and a refresh controller. The command queue is for storing the memory access requests. The refresh controller is coupled to the command queue and is operable to select an order of providing multi-bank refresh commands to sets of selected banks of the plurality of banks in the memory in response to lowest-cost estimates of the banks of the memory based on the memory access requests in the command queue.

Abstract: Systems and methods for building applications by automatically incorporating application performance data into the application build process are disclosed. By capturing build settings and performance data from prior applications being executed on different computing systems such as bare metal and virtualized cloud instances, a performance database may be maintained and used to predict build settings that improve application performance (e.g., on a specific computing system or computing system configuration).

Abstract: Automatic key rolling for link encryption is described. In accordance with the described techniques, data packets are encrypted at a first endpoint of a communication link using a first data encryption key. The encrypted data packets are communicated over the communication link to a second endpoint. A key rolling event that is known by both the first endpoint and the second endpoint is detected at the first endpoint. Responsive to detecting the key rolling event, the first data encryption key is rolled to a second data encryption key for encrypting data packets communicated over the communication link. In one or more implementations, the second endpoint is also configured to roll from the first data encryption key to the second data encryption key responsive to the key rolling event in order to decrypt data packets encrypted with the second data encryption key which are received from the first endpoint.

Abstract: Devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring after the build time: performing ray intersection tests, using the additional data generated during the build time, for the rays in the scene; and rendering the scene based on the ray intersection tests. Because the additional data is generated prior to render time, the additional data can be used to perform the ray intersection testing more efficiently.

Abstract: The disclosed computer-implemented method for automatically generating a printed circuit board design includes executing, by at least one processor based on input parameters, a grouping operation that identifies network shapes defining regions occupied by corresponding networks for one or more layers of an integrated circuit package. The method additionally includes identifying, by the at least one processor based on the identified network shapes, connections of the integrated circuit package. The method also includes automatically generating, by the at least one processor and based on the identified connections, a printed circuit board design. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.

Abstract: A technique for performing ray tracing operations is provided. The technique includes traversing a bounding volume hierarchy for a ray to arrive at a bounding box without use of a neural network; perform a feature vector lookup using modified polar coordinates characterizing the ray relative to the bounding box to obtain a set of feature vectors; and obtaining output with the neural network using the set of feature vectors.

Abstract: Structural thermal interfacing for lidded semiconductor packages, including: applying, to a periphery of a surface of a chip, a stiffening adhesive framing a center portion of the chip; applying, to the center portion of the chip, a thermal interface material; and applying a lid to the chip, wherein the lid contacts the stiffening adhesive and is thermally coupled to the chip via the thermal interface material after application to the chip.

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

Abstract: An optimized service-based pipeline includes a resource manager that receives a request that includes a description of a workload from a workload initiator such as an application. The resource manager identifies runtime utilization metrics of a plurality of processing resources, where the plurality of processing resources includes at least a first graphics processing unit (GPU) and a second GPU. The resource manager determines, based on the utilization metrics and one or more policies, a workload allocation recommendation for the workload. Thus, the workload initiator can determine whether placing a workload on a particular processing resource is preferable based on runtime behavior of the system and policies established of the workload.

Abstract: A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A rack is provided. In one aspect, a rack includes a horizontal tray, a vertical tray, and an L-shaped cable cartridge. The L-shaped cable cartridge includes connectors configured to connect to horizontal tray connectors on a first side of the horizontal tray and to vertical tray connectors on a second side of the vertical tray that is orthogonal to the first side. Further, the L-shaped cable cartridge includes cables connected to the connectors in the L-shaped cable cartridge to facilitate communication between the horizontal and vertical trays.