Patents Assigned to Advanced Micro Devices, Inc.
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Patent number: 11816037Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.Type: GrantFiled: December 12, 2019Date of Patent: November 14, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Steven Raasch, Andrew G. Kegel
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Patent number: 11816781Abstract: A processor shares path tracing data across sampling locations to amortize computations across space and time. The processor maps a group of sampling locations of a frame that are adjacent to each other in world-space to a cell of a hash table. Each cell of the hash table stores a list of reservoirs that are each associated with a ray that intersects the group of sampling locations from world-space. The processor resamples the reservoirs at the hash table by combining and re-using reservoirs across neighboring sampling locations and corresponding sampling locations of the previous frame to select a set of samples mapped to the cell. The processor then performs resampling of the selected set of samples to obtain a representative light sample to determine a value for the cell and renders the frame based on the value of the cell.Type: GrantFiled: June 22, 2021Date of Patent: November 14, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Guillaume Marie Boisse
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Patent number: 11809322Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.Type: GrantFiled: September 13, 2021Date of Patent: November 7, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton, Elizabeth M. Cooper, Ravindra N. Bhargava
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Patent number: 11809260Abstract: A method of operating a multiphase power supply includes identifying a least efficient phase of a plurality of phases in the multiphase power supply based on a comparison of a pulse width for each phase in the plurality of phases, and decreasing an amount of power supplied to a load by the identified least efficient phase.Type: GrantFiled: September 23, 2020Date of Patent: November 7, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Martin McAfee, David L Wigton
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Patent number: 11810891Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.Type: GrantFiled: March 2, 2021Date of Patent: November 7, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Milind S. Bhagavat
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Patent number: 11809558Abstract: A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is equal to the received packet size of the command packet. The command processor passes, based at least on determining a match between the received packet size and the expected packet size, the received command packet to the prefetch parser. Otherwise, the command processor passes, based at least on determining a mismatch between the received packet size and the expected packet size, one or more no-operation instructions to the prefetch parser.Type: GrantFiled: September 25, 2020Date of Patent: November 7, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Harry J. Wise, Alexander Fuad Ashkar, Manu Rastogi
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Patent number: 11809743Abstract: A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. A refresh control circuit monitors activate commands to be sent over the memory channel. In response to an activate command meeting a designated condition, the refresh control circuit identifies a candidate aggressor row associated with the activate command. A command is sent to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.Type: GrantFiled: September 21, 2020Date of Patent: November 7, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Kevin M. Brandl
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Patent number: 11809902Abstract: Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup dependency instruction including an indication to prioritize execution of the third workgroup has been executed.Type: GrantFiled: September 24, 2020Date of Patent: November 7, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Alexandru Dutu, Marcus Nathaniel Chow, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood
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Publication number: 20230351187Abstract: Systems, methods, and devices for pruning a convolutional neural network (CNN). A subset of layers of the CNN is chosen, and for each layer of the subset of layers, how salient each filter in the layer is to an output of the CNN is determined, a subset of the filters in the layer is determined based on the salience of each filter in the layer, and the subset of filters in the layer is pruned. In some implementations, the layers of the subset of layers of the CNN are non-contiguous. In some implementations, the subset of layers includes odd numbered layers of the CNN and excludes even numbered layers of the CNN. In some implementations, the subset of layers includes even numbered layers of the CNN and excludes odd numbered layers of the CNN.Type: ApplicationFiled: June 30, 2023Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Arun Coimbatore Ramachandran, Chandra Kumar Ramasamy, Prakash Sathyanath Raghavendra, Keerthan Shagrithaya
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Publication number: 20230351667Abstract: A technique for building a bounding volume hierarchy is disclosed. The technique includes performing a nearest neighbor search for a set of clusters to generate a set of nearest neighbors; without performing a global barrier operation, performing a merge operation for the set of clusters, based on the set of nearest neighbors to generate merge results for the set of clusters; and without performing a global barrier operation, outputting clusters for a level of the bounding volume hierarchy, based on the merge results.Type: ApplicationFiled: September 30, 2022Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventor: John Alexandre Tsakok
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Publication number: 20230350480Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: ApplicationFiled: June 23, 2023Publication date: November 2, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Publication number: 20230350696Abstract: Real time workload-based system adjustment is described. In accordance with the described techniques, a processor and a memory are operated according to first settings associated with a first workload. A second workload configured to utilize the processor and the memory is detected. The second workload is associated with second settings. Responsive to detecting the second workload, operation of the processor and the memory are adjusted to operate according to the second settings without rebooting.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Anil Harwani, William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Joshua Taylor Knight
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Publication number: 20230350715Abstract: Various timing parameter values for a memory system are changed and a workload is run using the changed timing parameter values resulting in workload performance values. The workload is run multiple times with different timing parameter values and the performance values generated by the workload are used to generate and output a performance indication that identifies how sensitive performance of the physical memory is to the one or more timing parameters. The parameter values generated by the workload are optionally used to predict what parameter value the workload would have generated for user selected timing parameter values (e.g., without running the workload).Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Joshua Taylor Knight, Jayesh Hari Joshi, Anil Harwani, Grant Evan Ley, Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra
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Publication number: 20230350484Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.Type: ApplicationFiled: April 21, 2023Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Publication number: 20230350591Abstract: Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Grant Evan Ley, Jayesh Hari Joshi, Amitabh Mehra, Jerry Anton Ahrens, Joshua Taylor Knight, Anil Harwani, William Robert Alverson
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Publication number: 20230350830Abstract: An apparatus and method for performing memory operations in memory stacks comprising receiving a memory operation request at a first memory controller, where the first memory controller is in included in a first logic die in communication with a first memory die of a first memory technology, from a processor via a first bus. The method further comprising, on a condition that the memory operation request is associated with a second memory technology, communicating the memory operation request to a second memory controller via a side bus, where the second memory controller is included in a second logic die in communication with a second memory die of the second memory technology, and, on a condition that the memory operation request is associated with the first memory technology, performing the memory operation request. The first and second logic dies and the first and second memory dies being stacked on the processor.Type: ApplicationFiled: March 13, 2023Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Dmitri Yudanov, Michael Ignatowski
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Publication number: 20230350485Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Vedula Venkata Srikant Bharadwaj, Shomit Das, Anthony T. Gutierrez, Vignesh Adhinarayanan
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Patent number: 11803473Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.Type: GrantFiled: November 8, 2021Date of Patent: October 31, 2023Assignee: Advanced Micro Devices, Inc.Inventors: John Kelley, Paul Moyer
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Patent number: 11803999Abstract: Systems, methods, and techniques utilize reinforcement learning to efficiently schedule a sequence of jobs for execution by one or more processing threads. A first sequence of execution jobs associated with rendering a target frame of a sequence of frames is received. One or more reward metrics related to rendering the target frame are selected. A modified sequence of execution jobs for rendering the target frame is generated, such as by reordering the first sequence of execution jobs. The modified sequence is evaluated with respect to the selected reward metric(s); and rendering the target frame is initiated based at least in part on the evaluating of the modified sequence with respect to the one or more selected reward metric(s).Type: GrantFiled: November 18, 2021Date of Patent: October 31, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Thomas Daniel Perry, Steven Tovey, Mehdi Saeedi, Andrej Zdravkovic, Zhuo Chen
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Patent number: 11803470Abstract: Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.Type: GrantFiled: December 22, 2020Date of Patent: October 31, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Amit Apte, Ganesh Balakrishnan, Ann Ling, Vydhyanathan Kalyanasundharam