Abstract: An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device.

Abstract: A system and method for providing video compression that includes encoding using an encoding engine a YUV stream wherein Y, U and V color values are encoded in parallel and patching together the Y, U and V color streams to form a compressed YUV output stream. The encoding engine further includes encoding each color value of the YUV stream in parallel using parallel encoding engines and a control engine for controlling operation all of the encoding engines in parallel. The YUV stream has an average bits per pixel value that varies from a first value to a second value that is double the first value. The encoding engine includes encoding the YUV stream in generally the same amount of time regardless of the average bits per pixel value.

Abstract: Methods and apparatuses are provided for controlling power consumption in a processor (or computational unit thereof). The method comprises monitoring power consumption in a processor (or computational unit) and determining that the power consumption of the processor (or computational unit) exceeds a threshold. Thereafter, instruction issuance if modified (such as by slowing or ceasing instruction issuance) within the processor (or computational unit) until the power consumption is below the threshold. The apparatus comprises a power consumption monitor for determining when power consumption within the processor exceeds a threshold. Upon that determination, a scheduler begins modify instruction issuance to one or more execution units until the power consumption is below the threshold. The modification of instruction issuance can be to slow instruction issuance or cease instruction issuance for a time period or until the power consumption is below the threshold.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value.

Abstract: Described are systems and methods for transmitting data at an aggregation device. The aggregation device includes a record queue and an output bypass queue. The data is received from an electronic device. A record is generated of the received data. The record is placed in the record queue. A determination is made that the record in the record queue is blocked. The blocked record is transferred from the record queue to the output bypass queue.

Abstract: A system and method of ensuring usage-based compliance based on a predicted model topology are disclosed. The system includes an information topology that extracts information from at least one information object, a daemon that operates to monitor interactions with at least one information object, an analyzer that performs a statistical-based pattern analysis using the monitored interactions, and a compliance policy that receives input from the information topology. The compliance policy is adjusted based on the analyzer and any new rules, and compares the actual state to the desired state. The method includes monitoring a file system to capture user interaction with the file system, performing statistical-based pattern analysis on the captured interactions, adjusting a compliance policy based on the statistical analysis and any new rules, inputting an information topology into the compliance policy, and comparing the actual state to a desired state that is based on the adjusted compliance policy.

Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Abstract: Described are a system and method for processing a media access control (MAC) address. A communication is established between a processing device and a network port of a data switching device. The data switching device assigns a MAC address to the processing device. The assigned MAC address is directly associated with the network port of the data switching device absent a learning mechanism.

Abstract: A hardware based memory allocation system in a computer includes: a memory module formatted with memory blocks; an input controller, in communications with the memory module and receiving a transfer request from a requestor, for transferring data from a source to the memory module; an output controller, in communications with the memory module and the input controller, for transferring data from the memory module to a destination; and a block allocator, in communications the input controller and the output controller, for maintaining a Block Descriptor Index (BDI) of Free List (FL) Addresses, each FL address pointing to a Block Descriptor Page (BDP) having a plurality of Memory Block (MB) addresses, each MB address pointing to a free memory block in the memory module.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: A system includes: a memory controller; a memory module with memory blocks in communication with the memory controller; an input controller in communication with the memory controller, where the memory controller notifies the input controller of a Next Address To Write corresponding with a Next Memory Block To Write in the memory module, each input block contains an address to a next block, and data is written to the is Memory Block To Write at the Next Address To Write in the memory module; and an output controller in communication with the other controllers, receives a starting address from the input controller of a first memory block to read from the memory module, a starting address is a Next Address To Read from a Next Memory Block To Read in the memory module, and the memory controller compares the Next Address To Write with the Next Address To Read.

Abstract: A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.

Abstract: The present disclosure relates to methods and systems for designing and fabricating an integrated circuit. In particular, a method includes electronically searching a virtual layout of an integrated circuit to locate a dummy polysilicon structure positioned between adjacent terminals of first and second MOSFET devices that are connected to different nodes of the integrated circuit. The method includes changing a configuration of the dummy polysilicon structure of the virtual layout to extend an active silicon region adjacent to the dummy polysilicon structure and to form an electrical connection between the dummy polysilicon structure and one of a supply voltage node and a ground node of the integrated circuit.

Abstract: A content addressable memory (CAM) suppresses an indication of a match in response to determining that the entry that stores data matching received compare data is the subject of a write operation. To suppress the indication, an address decoder decodes a write address associated with the write operation to determine the entry of the CAM that is the subject of the write operation, and provides control signaling indicative of the determined entry. The CAM uses the control signaling to suppress any match indications for the entry being written, thereby preventing erroneous match indications.

Abstract: Methods and systems for simulating a system model are provided. The method includes loading into a computing system the system model that includes a plurality of event generating device models and non-event generating device models, scheduling a next event for each of the event generating device models independent of the next event of each other of the device models, advancing time to an earliest of the scheduled next events that is scheduled at a host device, committing the earliest of the scheduled next events, and replacing the earliest of the scheduled next events with a new next event for the host device.

Abstract: A resonant clock network includes an inductor coupled to the clock network through a plurality of switches. When the clock network enters resonant mode, the turn-on of the switches to couple the inductor to the clock network is staggered. The clock network may be formed of multiple regions, each with its own inductor and switches. The turn-on of switches of each region may be staggered with respect to the turn-on off the switches of the other regions as well as to the turn-on of switches within a region. In addition to staggering the turn-on of the switches when entering the resonant mode, the switches may be turned off in a staggered manner when exiting the resonant mode of operation.

Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.

Abstract: Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued.

Abstract: A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit.