Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.

Abstract: Data reuse cache techniques are described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and is also stored to a data reuse cache communicatively coupled between the load-store unit and the execution unit. Upon receipt of a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.

Abstract: Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.

Abstract: One or more processing units, such as a graphics processing unit (GPU), execute an application. A resource manager selectively allocates a first memory portion or a second memory portion to the processing units based on memory access characteristics. The first memory portion has a first latency that is lower that a second latency of the second memory portion. In some cases, the memory access characteristics indicate a latency sensitivity. In some cases, hints included in corresponding program code are used to determine the memory access characteristics. The memory access characteristics can also be determined by monitoring memory access requests, measuring a cache miss rate or a row buffer miss rate for the monitored memory access requests, and determining the memory access characteristics based on the cache miss rate or the row buffer miss rate.

Abstract: A disclosed technique includes determining a plurality of per-pixel variable rate shading rates for a plurality of fragments; determining a coarse variable shading rate for a coarse variable rate shading area based on the plurality of per-pixel variable rate shading rates; and shading one or more fragments based on the plurality of fragments and based on the coarse variable shading rate.

Abstract: A method for managing operational costs associated with distributed computing. The method includes: creating, via a graphical user interface (GUI), a distributed computing team; linking a digital team wallet to the distributed computing team, wherein the digital team wallet is linked to a currency account; adding a member to the distributed computing team; allowing the member to purchase compute resource access from a plurality of compute resource providers using the digital team wallet; and notifying a team manager when funds in the digital team wallet reduce to at least a team threshold value.

Abstract: Systems, apparatuses, and methods for implementing a low power parallel matrix multiply pipeline are disclosed. In one embodiment, a system includes at least first and second vector register files coupled to a matrix multiply pipeline. The matrix multiply pipeline comprises a plurality of dot product units. The dot product units are configured to calculate dot or outer products for first and second sets of operands retrieved from the first vector register file. The results of the dot or outer product operations are written back to the second vector register file. The second vector register file provides the results from the previous dot or outer product operations as inputs to subsequent dot or outer product operations. The dot product units receive the results from previous phases of the matrix multiply operation and accumulate these previous dot or outer product results with the current dot or outer product results.

Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

Abstract: An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. The memory controller maintains and uses a page table to properly configure memory elements, such as banks in a memory module, for the next memory command, whether a PIM command or a non-PIM command. The page table tracks the status of memory elements as of the most recent memory command that was issued. The page table includes an “All Bank” entry that indicates the status of banks after processing the most recent PIM command. For example, the All Banks entry indicates whether all the banks have a row open and if so, specifies the open row for all the banks.

Abstract: Systems, apparatuses, and methods for performing color channel correlation detection are disclosed. A compression engine performs a color channel transform on an original set of pixel data to generate a channel transformed set of pixel data. An analysis unit determines whether to compress the channel transformed set of pixel data or the original set of pixel data based on performing a comparison of the two sets of pixel data. In one scenario, the channel transformed set of pixel data is generated by calculating the difference between a first pixel component and a second pixel component for each pixel of the set of pixel data. The difference is then compared to the original first pixel component for each pixel. If the difference is less than or equal to the original for a threshold number of pixels, then the analysis unit decides to apply the color channel transform prior to compression.

Abstract: A coherency management device receives requests to read data from or write data to an address in a main memory. On a write, if the data includes zero data, an entry corresponding to the memory address is created in a cache directory if it does not already exist, is set to an invalid state, and indicates that the data includes zero data. The zero data is not written to main memory or a cache. On a read, the cache directory is checked for an entry corresponding to the memory address. If the entry exists in the cache directory, is invalid, and includes an indication that data corresponding to the memory address includes zero data, the coherency management device returns zero data in response to the request without fetching the data from main memory or a cache.

Abstract: A memory system uses error detection codes to detect when errors have occurred in a region of memory. A count of the number of errors is kept and a notification is output in response to the number of errors satisfying a threshold value. The notification is an indication to a host (e.g., a program accessing or managing a machine learning system) that the threshold number of errors have been detected in the region of memory. As long as the number of errors that have been detected in the region of memory remains under the threshold number no notification need be output to the host.

Abstract: Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.

Abstract: Automatic generation of data layout instructions for locating data objects in memory that are involved in a sequence of operations for a computational task is described. In accordance with the described techniques, an interference graph is generated for the sequence of operations, where individual nodes in the interference graph represent data objects involved in the computational task. The interference graph includes edges connecting different pairs of nodes, such that an edge indicates the connected data objects are involved in a common operation of the sequence of operations. Weights are assigned to edges based on architectural characteristics of a system performing the computational task as well as a size of the data objects connected by an edge. Individual data objects are then assigned to locations in memory based on edge weights of edges connected to a node representing the data object, optimizing system performance during the computational task.

Abstract: Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.

Abstract: Methods and systems are disclosed for encoding a Morton code. Techniques disclosed comprise receiving location vectors associated with primitives, where the primitives are graphical elements spatially located within a three-dimensional scene. Techniques further comprise determining a code pattern comprising a prefix pattern and a base pattern, and, then, coding each of the location vectors according to the code pattern.

Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Abstract: Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.