Abstract: An integrated circuit system includes measuring capacitance for a base structure between a base gate and a base connector thereof, measuring capacitance for a test structure between a test gate and a test connector thereof, the test structure having the test gate, a test dielectric, and the test connector with the test dielectric extending thereunder, and determining a difference between the capacitances of the base structure and the test structure to determine parasitic capacitance for the base structure between the base gate and the base connector thereof.

Abstract: A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into one or more full-bit operations, when the full-bit mode is indicated, or one or more reduced-bit operations, when the reduced-bit mode is indicated.

Abstract: A device is provided for detecting delays of data due to over-temperature conditions, the device includes a first latch having a data input and a clock input and an output, and a first delay path including combinational logic, a first input coupled to the output of the first latch, and an output. The device further includes a second latch having a data input coupled to the output of the first delay path, a clock input coupled to the clock input of first latch, and an output, and a delay element having a data input coupled to the clock input of the first latch and an output. The device includes a third latch having a data input coupled to the output of the first delay path, a clock input coupled to the output of the delay element, and an output, and a comparator having a first input coupled to the output of the second latch, a second input coupled to the output of the third latch, and an output.

Abstract: A branch history value associated with a first branch instruction of a first set of instructions is determined. The branch history value represents a branch history of a program flow prior to the first branch instruction. A first branch prediction of the first branch instruction is determined based on the branch history value of the first branch instruction and a first identifier associated with first branch instruction. A second branch prediction of a second branch instruction of the first set of instructions based on the branch history value associated with the first branch instruction and a second identifier associated with the second branch instruction. The second branch instruction occurs subsequent to the first branch instruction in the program flow. A second set of instructions is fetched at the processing device based on at least one of the first branch prediction and the second branch prediction.

Abstract: A method for reducing power consumption in an integrated circuit and an integrated circuit having a power reduction feature. The integrated circuit has at least two functional circuit blocks and two upper supply rails. A first upper supply rail is coupled to the first functional circuit block and a second upper supply rail is coupled to the second functional circuit block. A lower supply rail is coupled to the first and second functional circuit blocks. In an active mode of operation, a first source of operating potential is electrically coupled to the first upper supply rail and a second source of operating potential is electrically coupled to the second upper supply rail. In an idle mode of operation, the first upper supply rail remains electrically coupled to the first source of operating potential and the second source of operating potential is electrically decoupled from the second functional circuit block.

Abstract: A WLAN (Wireless Local Area Network) transmitter or another data communications apparatus is provided that includes a transmission section that is configured to generate signals to be transmitted, and a control section that is connected to the transmission section to control the transmission section dependent on at least two transmission parameters. The control section comprises a state transition controller that is configured to step through a plurality of predefined control states. The control section is configured to apply different transmission parameter modification mechanisms in different control states. The state transition controller is configured to determine the respective next control states based on transmission success and failure statistics.

Abstract: By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract: In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to be intercepted during execution of a guest. Responsive to the intercept indication and further responsive to detecting the event, execution circuitry in the processor is configured to exit the guest. In another embodiment, a method comprises: detecting an event that would cause a processor to transition to a first mode, wherein first code is to be executed in the first mode; and causing the first code to be executed in a guest responsive to the detecting. In still another embodiment, a computer accessible medium comprising instructions which when executed in response to detecting the event, cause the first code to be executed in a guest.

Abstract: A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

Abstract: By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectivity of the contact structure may be increased by a modification of the etch behavior of the exposed portion of the contact etch stop layer.

Abstract: A system for testing integrated circuit storage structures on a semiconductor wafer. A test IC manufactured on a semiconductor wafer includes a test storage structure such as a random access memory structure, for example, and an access controller including one or more clock sources. In various embodiments, the clock sources may include a ring oscillator and a pulse width generator. These clock sources may be programmable to provide a clock signal having a variety of frequencies for accessing the storage structure. In one embodiment, the frequencies provided by the access controller may be higher than a frequency that can be supplied to the wafer from ATE. In another embodiment, the pulse width generator may be programmable to provide a pulse train having a variety of duty cycles.

Abstract: Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel region in the semiconductor substrate so that the stressed dummy gate induces a stress in the channel region. Regions of the semiconductor substrate adjacent the channel are processed to maintain the stress to the channel region and the stressed dummy gate electrode is replaced with a permanent gate electrode.

Abstract: By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precursor solution, which may exhibit a substantially self-aligned and self-limiting deposition behavior.

Abstract: By estimating the processing rate on the basis of capacity factors, which are classified with respect to process recipes, i.e., technology nodes, and process tool groups, a fast response to various conditions may be accomplished, thereby providing significantly enhanced flexibility in estimating the productivity and rentability of a manufacturing environment.

Abstract: The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

Abstract: A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.

Abstract: A method is disclosed for singulating die containing semiconductor device whereby a trench is etched at a first scribe region of a wafer comprising semiconductor devices, and sawing the wafer within the trench.

Abstract: Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, where the network interface system may be fabricated as a single integrated circuit chip. Systems and methods are disclosed wherein out-of-order writing is used to improve throughput for the security system on the receive end.

Abstract: A method and apparatus are provided. The method includes establishing a communication channel between a first transceiver and a second transceiver in low power mode, and determining a training parameter using the communication channel. The method also includes performing training in response to determining the training parameter. The apparatus, capable of communicating with a transceiver, includes a first and second logic. The first logic is capable of establishing a communication channel with the transceiver in a low power mode. The second logic is capable determining a training parameter using the communication channel, and providing the training parameter to the transceiver.