Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.

Abstract: The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.

Abstract: Metal pillars (18) having diameters of less than about 1.0 .mu.m are grown in vias (16) in dielectric layers (14) between metal layers (12, 22) by a process comprising: (a) forming a first metal layer (12) at a first temperature and patterning the metal layer; (b) forming the dielectric layer to encapsulate the first patterned metal layer, the dielectric layer having a compressive stress of at least about 100 MegaPascal and being formed at a second temperature; (c) opening vias in the dielectric layer to exposed underlying portions of the patterned metal layer, the vias being less than about 1.0 .mu.m in diameter; (d) heating the semiconductor wafer at a temperature that is greater than either the first or second temperatures to induce growth of metal in the vias from the metal layer; and (e) forming the second metal layer (22) over the dielectric layer to make contact with the metal pillars.

Abstract: A layered dielectric structure is provided, which separates a first layer of metal interconnects from each other in semiconductor devices and also separates the first layer from a second, overlying layer of metal interconnects for making electrical contact to the first layer of metal interconnects. The layered dielectric structure comprises: (a) a layer of an organic spin-on-glass material filling gaps between metal interconnects in the first layer of metal interconnects; (b) a layer of an inorganic spin-on-glass material to provide planarization to support the second layer of metal interconnects; and (c) a layer of a chemically vapor deposited oxide separating the organic spin-on-glass layer and the inorganic spin-on-glass layer. The layered dielectric structure provides capacitances on the order of 3.36 to 3.46 in the vertical direction and is about 3.2 in the horizontal direction. This is a reduction of 10 to 15% over the prior art single dielectric layer, using existing commercially available materials.

Abstract: An improved process is provided for forming a multilayer structure (18) suitable for tape automated bonding thereto or for forming contacts. In the process, a first layer (12) of aluminum is formed on a substrate (10), a second layer (14) of a TiW alloy is formed on the first layer of aluminum, and a third layer (16) of gold is formed on the second layer of the TiW alloy, to which third layer of gold bonding is done. The improvement comprises annealing the second layer of the TiW alloy in an inert atmosphere at a temperature less than about 500.degree. C. for a period of time sufficient to form a film of an Al--TiW phase (20), believed to comprise TiAl.sub.3, at the interface between the first layer of aluminum and the second layer of the TiW alloy. The annealing is done prior to forming the third layer of gold on the second layer of the TiW alloy.