Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.

Abstract: A data compressor for a lossless data compression system includes a hardware aware encoder and a key signal processor. The hardware aware encoder encodes a data value signal into a key signal according to a key assignment formed by determining a number of data values of a value space in which each data value comprises a plurality of bits, determining a size of the key to encode the number of data values of the value space, grouping the data values into a plurality of groups based on a fewest number of bit differences between data values in each group, and assigning fragments of the key based on a fewest number of bits that can differentiate groups based on remaining bits of the data values. The key signal processor has an output adapted to be coupled to a medium for providing a representation of the key signal to the output.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract: A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel.

Abstract: In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device having capability to compensate for a clock frequency mismatch. A device includes an interconnect interface comprising a transmit port and a receive port, and a configuration structure. The configuration structure comprises a capability field to store a value indicating whether the device has a capability to compensate for a clock frequency mismatch, and an enable field. The device further includes a packet control module to configure a rate of insertion of clock mismatch compensation symbols by the transmit port into a data stream responsive to a value stored at the enable field.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method and apparatus are described for performing sprinting in a processor. An analyzer in the processor may monitor thermal capacity remaining in the processor while not sprinting. When the remaining thermal capacity is sufficient to support sprinting, the analyzer may perform sprinting of a new workload when a benefit derived by sprinting the new workload exceeds a threshold and does not cause the remaining thermal capacity in the processor to be exhausted. The analyzer may perform sprinting of the new workload in accordance with sprinting parameters determined for the new workload. The analyzer may continue to monitor the remaining thermal capacity while not sprinting when the benefit derived by sprinting the new workload does not exceed the threshold.

Abstract: A method of controlling voltage in a circuit is provided. Within the circuit, a block of an electrical component provides an indication that it desires to switch states (such as from off to on, on to off, or from one speed to another). The change in states requires a different current draw by the electrical component block. The indication is received by an electrical component that controls the voltage of the circuit. The electrical component that controls the voltage then issues a signal granting permission for the electrical component block to switch states. This permission signal is received by the electrical component and the electrical component block changes state.

Abstract: A method of assembling a semiconductor chip device is provided. The method includes providing a first circuit board that has a plurality of thermally conductive vias. A second circuit board is mounted on the first circuit board over and in thermal contact with the thermally conductive vias. The second circuit board includes first side facing the first circuit board and a second and opposite side.

Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes processing units each of which operates with respective operating parameters. Temperature sensors are included to measure a temperature of the one or more processing units during operation. A power manager determines a calculated power value independent of thermal conditions and current draw. The power manager reads each of a first thermal design power (TDP) value for the processing units and a second TDP value for a platform housing the semiconductor chip. The power manager determines a ratio of the first TDP value to the second TDP value. Additionally, the power manager determines another ratio of the first TDP value to the calculated power value. Using the measured temperature, the ratios and the calculated power value, the power manager determines a manner to adjust the operating parameters.

Abstract: A lever mechanism facilitates coupling of a sliding board and a connector. A sliding board is partially enclosed by a sliding board enclosure, such that the sliding board is slidable relative to the enclosure. A pair of pivot levers is disposed between the sliding board and the enclosure. Each pivot lever is connected at a proximal end to the enclosure and at a pivot point to the sliding board. A distal end of the pivot lever is removably engageable with a second circuit board. The lever mechanism translates a pushing force on the enclosure to a pulling force on the sliding board, aligning and eventually coupling the sliding board with the connector.

Abstract: A die-stacked memory device implements an integrated QoS manager to provide centralized QoS functionality in furtherance of one or more specified QoS objectives for the sharing of the memory resources by other components of the processing system. The die-stacked memory device includes a set of one or more stacked memory dies and one or more logic dies. The logic dies implement hardware logic for a memory controller and the QoS manager. The memory controller is coupleable to one or more devices external to the set of one or more stacked memory dies and operates to service memory access requests from the one or more external devices. The QoS manager comprises logic to perform operations in furtherance of one or more QoS objectives, which may be specified by a user, by an operating system, hypervisor, job management software, or other application being executed, or specified via hardcoded logic or firmware.

Abstract: A locally asynchronous logic circuit includes an input latch; a synchronous-to-asynchronous control circuit having an input for receiving a first clock signal, a first output coupled to the latch enable input of the input latch, and a second output for providing a start signal; a predetermined number of stages coupled between the output of the input latch and an output of the locally asynchronous logic circuit, each stage having an asynchronous functional circuit and an associated completion circuit having an input for receiving a corresponding start signal and an output for providing a corresponding done signal; and an asynchronous-to-synchronous control circuit having a first input for receiving a done signal of a preceding stage, and an output for providing a valid signal. The asynchronous-to-synchronous control circuit activates said first valid signal to indicate said output of the locally asynchronous logic circuit is valid.

Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.

Abstract: A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives. A hull shader is modified to compute values used by the new shaders to perform tessellation algorithms. This approach provides parallelism and customizability to the presently static tessellation engine implementation.

Abstract: Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold.

Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature headroom utilizing temperature values based on worst-case ambient temperature. When the measured temperature does not exceed the threshold, the power manager determines the temperature headroom utilizing at least one temperature value based on room ambient temperature. Following, the power manager adjusts the respective operating parameters based on at least the temperature headroom.

Abstract: Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.

Abstract: An apparatus includes a printed circuit board including a connector footprint comprising a first footprint portion operative to receive a first connector portion and a second footprint portion operative to receive a second connector portion. The first footprint portion is compliant with a first communications link type and the first and second footprint portions are jointly compliant with a second communications link type. The printed circuit board includes first conductive traces coupled to the first footprint portion and a first device footprint. The first conductive traces are selectively configurable according to a selected one of the first and second communications link types. The printed circuit board includes a second conductive traces coupled to the second footprint portion and the first device footprint. in at least one embodiment of the apparatus, the first communications link type is AC-coupled and the second communications link type is DC-coupled.

Abstract: A processor system presented here has a plurality of execution cores and a plurality of stack caches, wherein each of the stack caches is associated with a different one of the execution cores. A method of managing stack data for the processor system is presented here. The method maintains a stack cache manager for the plurality of execution cores. The stack cache manager includes entries for stack data accessed by the plurality of execution cores. The method processes, for a requesting execution core of the plurality of execution cores, a virtual address for requested stack data. The method continues by accessing the stack cache manager to search for an entry of the stack cache manager that includes the virtual address for requested stack data, and using information in the entry to retrieve the requested stack data.