Patents Assigned to Advanced Micro Devices (Shanghai) Co., Ltd.
  • Patent number: 10656951
    Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: May 19, 2020
    Assignees: ADVANCED MICRO DEVICES, INC., ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
    Inventors: Jiasheng Chen, YunXiao Zou, Bin He, Angel E. Socarras, QingCheng Wang, Wei Yuan, Michael Mantor
  • Patent number: 10198283
    Abstract: A request is sent from a new virtual function (VF) to a physical function for requesting the initialization of the new VF. The controlling physical function and the new VF establish a two-way communication channel that to start and end the VF's exclusive accesses to registers in a configuration space. The physical function uses a timing control to monitor that exclusive register access by the new VF is completed within a predetermined time period. The new VF is only granted a predetermined time period of exclusive access to complete its initialization process. If the exclusive access period is timed out, the controlling physical function can terminate the VF to prevent GPU stalls.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: February 5, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices (Shanghai) Co., LTD.
    Inventors: Jeffrey G. Cheng, Yinan Jiang, Guangwen Yang, Kelly Donald Clark Zytaruk, LingFei Liu, XiaoWei Wang
  • Publication number: 20180102296
    Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 12, 2018
    Applicant: Advanced Micro Device (Shanghai) Co., Ltd.
    Inventors: I-Tseng LEE, Yu-Ling HSIEH
  • Patent number: 9870969
    Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 16, 2018
    Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
    Inventors: I-Tseng Lee, Yu-Ling Hsieh
  • Patent number: 9214438
    Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 15, 2015
    Assignee: Advanced Micro Devices (Shanghai) Co., Ltd.
    Inventors: I-Tseng Lee, Yi Hsiu Liu
  • Patent number: 8994191
    Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: March 31, 2015
    Assignee: Advanced Micro Devices (Shanghai) Co. Ltd.
    Inventors: I-Tseng Lee, Yi Hsiu Liu
  • Publication number: 20140246223
    Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 4, 2014
    Applicant: Advanced Micro Devices (Shanghai) Co., Ltd.
    Inventors: I-Tseng Lee, Yu-Ling Hsieh