Abstract: Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system.

Abstract: In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

Abstract: The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

Abstract: A method and system for varying sampling frequency to avoid software harmonics when sampling digital power indicators are described herein. A power monitor may repetitively sample, at a variable sampling rate based on a variable delay time, multiple signals of an IC device to obtain energy values. The variable delay time may be based on a pseudo-random value or a predictable value. The variable delay time may indicate a number of delay cycles that may be inserted between the repetitive samples of the energy values. The variable number of delay cycles between energy value samples may produce a variable sampling rate. A variable sampling rate may avoid alignment with software harmonics which can cause an inaccurate representation of power consumption. The multiple samples obtained by repetitively sampling energy value for the portion of the IC may be summed to generate a cumulative energy value for the portion of the IC.

Abstract: A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free.

Abstract: A circuit for use in a computing system including a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, the autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.

Abstract: Data stored in SRAM cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the Bias Temperature Instability (BTI) degradation to be symmetric, thereby not degrading the Static Noise Margin (SNM) degradation of the cells. The data stored in memory locations is flipped by reading out the data, inverting the read out data, and writing the inverted read out data into the memory locations until the memory locations of the SRAM have been read out and written. When the memory operates in flipped mode, data read from and written into the memory is inverted to maintain transparency to the memory user. After operating the data in flipped mode for a period of time, the flipped data stored in the memory is reflipped to operate in the non-flipped mode.

Abstract: A method, an apparatus, and a non-transitory computer readable medium for tracking prefetches generated by a stride prefetcher are presented. Responsive to a prefetcher table entry for an address stream locking on a stride, prefetch suppression logic is updated and prefetches from the prefetcher table entry are suppressed when suppression is enabled for that prefetcher table entry. A stride is a difference between consecutive addresses in the address stream. A prefetch request is issued from the prefetcher table entry when suppression is not enabled for that prefetcher table entry.

Abstract: A circuit includes memory retiling methods which distribute image information among a plurality of memory channels producing reconfigured image information distributed among a subset of the plurality of memory channels allowing memory channels outside of the subset to be placed into a power save mode to reduce power consumption. Additional methods are disclosed for further reductions in power consumption.

Abstract: A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.

Abstract: We report methods, integrated circuit devices, and fabrication processes relating to power management transitions of multiple compute units sharing a cache. One method includes indicating that a first compute unit of a plurality of compute units of an integrated circuit device is attempting to enter a low power state, determining if the first compute unit is the only compute unit of the plurality in a normal power state, and in response to determining the first compute unit is the only compute unit in the normal power state: saving a state of a shared cache unit of the integrated circuit device, flushing at least a portion of a cache of the shared cache unit, repeating the flushing until either a second compute unit exits the low power state or the cache is completely flushed, and permitting the first compute unit to enter the low power state.

Abstract: Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.

Abstract: A processor, a method and a computer-readable storage medium for encrypting a return address are provided. The processor comprises hardware logic configured to encrypt an instruction pointer and push the encrypted instruction pointer onto a stack. The logic is further configured to retrieve the encrypted instruction pointer from the stack, decrypt the instruction pointer and redirect execution to the decrypted instruction pointer.

Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Abstract: For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.

Abstract: One or more lines of a cache are prefetched according to a first prefetch routine while training a prefetcher to prefetch one or more lines of the cache according to a second prefetch routine. In response to determining that the prefetcher has been trained, one or more lines of the cache may be prefetched according to the second prefetch routine.

Abstract: A circuit with built-in self test (BIST) capability includes a master BIST controller, a plurality of slave BIST controllers, and a collector. The master BIS controller issues test instructions in response to a master resume input signal. The plurality of slave BIST controllers is coupled to the master BIST controller. Each slave BIST controller is adapted to perform a test on a functional circuit in response to a test instruction and to provide a resume signal at a conclusion of the test. The collector receives a corresponding resume signal from each of the multiple slave BIST controllers after the master BIST controller issues the test instruction, and subsequently provides the master resume signal in response to an activation of all of the corresponding resume signals.

Abstract: A system, method and computer program product to store tag blocks in a tag buffer in order to provide early row-buffer miss detection, early page closing, and reductions in tag block transfers. A system comprises a tag buffer, a request buffer, and a memory controller. The request buffer stores a memory request having an associated tag. The memory controller compares the associated tag to a plurality of tags stored in the tag buffer and issues the memory request stored in the request buffer to either a memory cache or a main memory based on the comparison.