Abstract: A method and apparatus for additive range reduction are disclosed. A constant may be pre-stored in a look-up table (LUT), and at least one section of the constant may be retrieved from the LUT for generating a product of an input argument and the constant such that a precision of the product may be controlled in any granularity. For a trigonometric function, 2/? is stored in the LUT, and at least one section of 2/? may be retrieved from the LUT. The argument is multiplied with the retrieved sections of 2/?. The retrieved sections are determined to correctly generate the two least significant bits (LSBs) of an integer portion and a scalable number of most significant bits of the multiplication result. An output of the trigonometric function is generated for the argument with a fractional portion of the multiplication result based on two LSBs of the integer portion of the multiplication result.

Abstract: A communication device includes a data source that generates data for transmission over a bus, and that further includes a data encoder coupled to receive and encode outgoing data. The encoder further includes a coupling toggle rate (CTR) calculator configured to calculate a CTR for the outgoing data, a threshold calculator configured to determine an expected value of the CTR as a threshold value, a comparator configured to compare the calculated CTR to the threshold value wherein the comparison is used to determine whether to perform an encoding step by an encoding block configured to selectively encode said data. A method according to one embodiment includes determining and comparing a CTR and an expected CTR to determine whether to encode the outgoing data. Any one of a plurality different coding techniques may be used including bus inversion.

Abstract: A variable series resistance termination circuit for wireline serial link transceivers is provided. Some embodiments include a pad for coupling to a wireline serial link and a termination circuit. The termination circuit includes a plurality of resistive components coupled in series with the pad and a plurality of switches. Each switch is to couple one or more of the plurality of resistive components in series between the pad and a termination voltage node when the switch is closed. A subset of the plurality of switches can be selectively closed to establish a resistive component of an impedance of the termination circuit.

Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.

Abstract: Methods, systems, and computer program products are provided for minimizing latency in a implementation where a peripheral device is used as a capture device and a compute device such as a GPU processes the captured data in a computing environment. In embodiments, a peripheral device and GPU are tightly integrated and communicate at a hardware/firmware level. Peripheral device firmware can determine and store compute instructions specifically for the GPU, in a command queue. The compute instructions in the command queue are understood and consumed by firmware of the GPU. The compute instructions include but are not limited to generating low latency visual feedback for presentation to a display screen, and detecting the presence of gestures to be converted to OS messages that can be utilized by any application.

Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.

Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory.

Abstract: A system has a plurality of functional modules including a first functional module and one or more other functional modules. The first functional module includes an embedded memory element and is configurable in a plurality of modes including a first mode and a second mode. When the first functional module is in the first mode, access to the embedded memory element is limited to the first functional module. At least one of the one or more other functional modules is provided with access to the embedded memory element based at least in part on the first functional module being in the second mode.

Abstract: A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.

Abstract: Embodiments of the present invention are directed to improving the performance of anti-aliased image rendering. One embodiment is a method of rendering a pixel from an anti-aliased image. The method includes: storing a first set and a second set of samples from a plurality of anti-aliased samples of the pixel respectively in a first memory and a second memory; and rendering a determined number of said samples from one of only the first set or the first and second sets. Corresponding system and computer program product embodiments are also disclosed.

Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: Methods, devices, and systems for managing performance of a processor having multiple compute units. An effective number of the multiple compute units may be determined to designate as having priority. On a condition that the effective number is nonzero, the effective number of the multiple compute units may each be designated as a priority compute unit. Priority compute units may have access to a shared cache whereas non-priority compute units may not. Workgroups may be preferentially dispatched to priority compute units. Memory access requests from priority compute units may be served ahead of requests from non-priority compute units.

Abstract: A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.

Abstract: An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.

Abstract: A server system includes a plurality of stacked modular computing structures. Each modular computing structure includes a circuit board comprising a computing resource, an air-fluid heat exchange structure comprising a first set of pipe segments, and a cold plate structure attached to a second set of pipe segments of the modular computing structure. The first set of pipe segments of each modular computing structure interfaces with the first set of pipe segments of at least one adjacent modular computing structure to form a corresponding section of a first fluid circulation loop. The second set of pipe segments of each modular computing structure interfaces with the second set of pipe segments of at least one adjacent modular computing structure to form a corresponding section of a second fluid circulation loop.

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

Abstract: Briefly, methods and apparatus to rebalance workloads among processing cores utilizing a hybrid work donation and work stealing technique are disclosed that improve workload imbalances within processing devices such as, for example, GPUs. In one example, the methods and apparatus allow for workload distribution between a first processing core and a second processing core by providing queue elements from one or more workgroup queues associated with workgroups executing on the first processing core to a first donation queue that may also be associated with the workgroups executing on the first processing core. The method and apparatus also determine if a queue level of the first donation queue is beyond a threshold, and if so, steal one or more queue elements from a second donation queue associated with workgroups executing on the second processing core.

Abstract: A method and apparatus for performing a top-down Breadth-First Search (BFS) includes performing a first determination whether to convert to a bottom-up BFS. A second determination is performed whether to convert to the bottom-up BFS, based upon the first determination being positive. The bottom-up BFS is performed, based upon the first determination and the second determination being positive. A third determination is made whether to convert from the bottom-up BFS to the top-down BFS, based upon the third determination being positive.

Abstract: The present application describes embodiments of techniques for picking a data array lookup request for execution in a data array pipeline a variable number of cycles behind a corresponding tag array lookup request that is concurrently executing in a tag array pipeline. Some embodiments of a method for picking the data array lookup request include picking the data array lookup request for execution in a data array pipeline of a cache concurrently with execution of a tag array lookup request in a tag array pipeline of the cache. The data array lookup request is picked for execution in response to resources of the data array pipeline becoming available after picking the tag array lookup request for execution. Some embodiments of the method may be implemented in a cache.

Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.