Patents Assigned to Advanced Micro Devices
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Patent number: 12015412Abstract: A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.Type: GrantFiled: December 1, 2022Date of Patent: June 18, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Srikanth Reddy Gruddanti, Pradeep Jayaraman, Ramon A. Mangaser, Prasant Kumar Vallur, Krishna Reddy Mudimela Venkata, David H. McIntyre
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Patent number: 12014442Abstract: A primary processing unit includes queues configured to store commands prior to execution in corresponding pipelines. The primary processing unit also includes a first table configured to store entries indicating dependencies between commands that are to be executed on different ones of a plurality of processing units that include the primary processing unit and one or more secondary processing units. The primary processing unit also includes a scheduler configured to release commands in response to resolution of the dependencies. In some cases, a first one of the secondary processing units schedules the first command for execution in response to resolution of a dependency on a second command executing in a second one of the secondary processing units. The second one of the secondary processing units notifies the primary processing unit in response to completing execution of the second command.Type: GrantFiled: December 19, 2019Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Rex Eldon McCrary
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Patent number: 12014527Abstract: Methods, devices, and systems for compressing and decompressing a stream of indices associated with graphics primitives. A group of delta values is determined based on a group of indices of the stream of indices. The group of delta values is compared to delta values in a lookup table. The group of indices is compressed based on an entry in the lookup table if the group of delta values matches all delta values in the entry, otherwise, the group of indices is compressed based on variable-length encoding.Type: GrantFiled: February 26, 2021Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Kiia Kallio, Mika Tuomi, Ruijin Wu, Anirudh R. Acharya
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Patent number: 12013810Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.Type: GrantFiled: September 29, 2022Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Matthaeus G. Chajdas
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Patent number: 12014208Abstract: Techniques for executing shader programs with divergent control flow on a single instruction multiple data (“SIMD”) processor are disclosed. These techniques includes detecting entry into a divergent section of a shader program and, for the work-items that enter the divergent section, placing a task entry into a task queue associated with the target of each work-item. The target is the destination, in code, of any particular work-item, and is also referred to as a code segment herein. The task queues store task entries for code segments generated by different (or the same) wavefronts. A command processor examines task lists and schedules wavefronts for execution by grouping together tasks in the same task list into wavefronts and launching those wavefronts. By grouping tasks from different wavefronts together for execution in the same front, serialization of execution is greatly reduced or eliminated.Type: GrantFiled: June 29, 2018Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Maxim V. Kazakov
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Patent number: 12014213Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.Type: GrantFiled: September 9, 2019Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sonu Arora, Daniel L. Bouvier
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Patent number: 12013752Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.Type: GrantFiled: June 16, 2022Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Publication number: 20240193097Abstract: Address translation is performed to translate a virtual address targeted by a memory request (e.g., a load or memory request for data or an instruction) to a physical address. This translation is performed using an address translation buffer, e.g., a translation lookaside buffer (TLB). One or more actions are taken to reduce data access latencies for memory requests in the event of a TLB miss where the virtual address to physical address translation is not in the TLB. Examples of actions that are performed in various implementations in response to a TLB miss include bypassing level 1 (L1) and level 2 (L2) caches in the memory system, and speculatively sending the memory request to the L2 cache while checking whether the memory request is satisfied by the L1 cache.Type: ApplicationFiled: December 9, 2022Publication date: June 13, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, John Kalamatianos
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Publication number: 20240192760Abstract: A disclosed technique includes in response to a trigger to power a functional element of a device to a lower power state, operating a set of backup state elements for the functional element in a lower power mode; and resuming operation of the functional element and the backup state elements in a higher power state.Type: ApplicationFiled: December 13, 2022Publication date: June 13, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Donny Yi, Karthik Rao
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Publication number: 20240192858Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.Type: ApplicationFiled: December 12, 2022Publication date: June 13, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Aaron D. Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
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Patent number: 12008237Abstract: An apparatus and method for designing memory macro blocks. A memory includes one or more memory banks, each with one or more arrays and input/output (I/O) blocks used to perform read accesses and write accesses. An array that utilizes multiple memory bit cells, and the I/O blocks are placed in a manner that they are abutting one another. The layout of the memory bit cells and the I/O blocks use a same subset of parameters of a semiconductor fabrication process. As a result, the memory bank does not include the placement of any boundary cells, which are used to improve yield of semiconductor layout. By skipping the use of the boundary cells, the dimensions of the memory bank are reduced, and layout density increases. Additionally, the memory bit cells use one or more p-type devices for one or more read pass gates.Type: GrantFiled: April 19, 2022Date of Patent: June 11, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Kurt M. English, Charwak Suresh Apte
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Patent number: 12009047Abstract: The disclosed computing device includes a cache memory and at least one processor coupled to the cache memory. The at least one processor is configured to copy data written to one or more nonredundant wordlines of the cache memory to one or more redundant wordlines of the cache memory. The at least one processor is additionally configured to detect a mismatch between data read from the one or more nonredundant wordlines and data stored in the one or more redundant wordlines. The at least one processor is also configured to perform a remediation action in response to detecting the mismatch. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: September 30, 2022Date of Patent: June 11, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Patrick James Shyvers
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Patent number: 12008378Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.Type: GrantFiled: April 10, 2023Date of Patent: June 11, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Varun Agrawal, Yasuko Eckert
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Patent number: 12009025Abstract: A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.Type: GrantFiled: June 25, 2021Date of Patent: June 11, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Tawfik Ahmed, Andrew J. Robison, Russell J. Schreiber
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Patent number: 12008401Abstract: Automatic central processing unit (CPU) usage optimization includes: monitoring performance activity of a workload comprising a plurality of threads; and modifying a resource allocation of a plurality of cores for the plurality of threads based on the performance activity.Type: GrantFiled: December 20, 2019Date of Patent: June 11, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Anil Harwani, Amitabh Mehra, William R. Alverson, Grant E. Ley, Jerry A. Ahrens, Kenneth Mitchell
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Patent number: 12007928Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.Type: GrantFiled: May 23, 2023Date of Patent: June 11, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Jason R. Talbert
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Patent number: 12008371Abstract: Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution.Type: GrantFiled: August 12, 2022Date of Patent: June 11, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Andrew G. Kegel
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Patent number: 12001237Abstract: Systems, methods, and devices for performing pattern-based cache block compression and decompression. An uncompressed cache block is input to the compressor. Byte values are identified within the uncompressed cache block. A cache block pattern is searched for in a set of cache block patterns based on the byte values. A compressed cache block is output based on the byte values and the cache block pattern. A compressed cache block is input to the decompressor. A cache block pattern is identified based on metadata of the cache block. The cache block pattern is applied to a byte dictionary of the cache block. An uncompressed cache block is output based on the cache block pattern and the byte dictionary. A subset of cache block patterns is determined from a training cache trace based on a set of compressed sizes and a target number of patterns for each size.Type: GrantFiled: September 23, 2020Date of Patent: June 4, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Matthew Tomei, Shomit N. Das, David A. Wood
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Patent number: 12002541Abstract: A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.Type: GrantFiled: June 30, 2022Date of Patent: June 4, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron John Nygren, Michael John Litt, Karthik Gopalakrishnan, Tsun Ho Liu
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Patent number: 12002128Abstract: Content feedback based on region of view, including: determining, for a user of a recipient device receiving content from a presenting device, a region of view of the content associated with the user; generating, based on the region of view, a visual overlay; and displaying, by the presenting device, the visual overlay applied to the content.Type: GrantFiled: July 19, 2021Date of Patent: June 4, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Roto Le
