Patents Assigned to Advanced Micro Devices
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Patent number: 11880277Abstract: Selecting an error correction code type for a memory device includes: selecting, by the memory device in dependence upon predefined selection criteria, one of a plurality of error correction code types and carrying out memory access requests utilizing the selected error correction code type.Type: GrantFiled: September 25, 2019Date of Patent: January 23, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Patent number: 11880310Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.Type: GrantFiled: December 16, 2021Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Paul Moyer, John Kelley
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Patent number: 11881393Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.Type: GrantFiled: September 29, 2021Date of Patent: January 23, 2024Assignee: Advanced micro devices, inc.Inventor: Richard T. Schultz
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Patent number: 11880312Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.Type: GrantFiled: November 30, 2021Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Kishore Punniyamurthy, SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov, Ganesh Dasika, Jagadish B Kotra
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Patent number: 11880610Abstract: A cluster compute server stores different types of data at different storage volumes in order to reduce data duplication at the storage volumes. The storage volumes are categorized into two classes: common storage volumes and dedicated storage volumes, wherein the common storage volumes store data to be accessed and used by multiple compute nodes (or multiple virtual servers) of the cluster compute server. The dedicated storage volumes, in contrast, store data to be accessed only by a corresponding compute node (or virtual server).Type: GrantFiled: November 16, 2020Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Mauricio Breternitz, Jr., Leonardo Piga
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Patent number: 11881450Abstract: A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets such as two different power rails, two different control signals, or two different data signals. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. In high voltage regions, a MIM capacitor has one or more intermediate metal plates formed as floating plates between electrode metal plates. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit.Type: GrantFiled: October 25, 2021Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Regina Tien Schmidt
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Patent number: 11880715Abstract: Methods and systems for load balancing in a neural network system using metadata are disclosed. Any one or a combination of one or more kernels, one or more neurons, and one or more layers of the neural network system are tagged with metadata. A scheduler detects whether there are neurons that are available to execute. The scheduler uses the metadata to schedule and load balance computations across compute resources and available resources.Type: GrantFiled: April 5, 2021Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Nicholas Malaya, Yasuko Eckert
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Publication number: 20240020173Abstract: Methods and systems are disclosed for distribution of a workload among nodes of a NUMA architecture. Techniques disclosed include receiving the workload and data batches, the data batches to be processed by the workload. Techniques disclosed further include assigning workload processes to the nodes according to a determined distribution, and, then, executing the workload according to the determined distribution. The determined distribution is selected out of a set of distributions, so that the execution time of the workload, when executed according to the determined distribution, is minimal.Type: ApplicationFiled: July 12, 2022Publication date: January 18, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Aditya Chatterjee
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Patent number: 11874783Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.Type: GrantFiled: December 21, 2021Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, Amit P. Apte, Eric Christopher Morton, Ganesh Balakrishnan, Ann M. Ling
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Patent number: 11875197Abstract: Systems, apparatuses, and methods for managing a number of wavefronts permitted to concurrently execute in a processing system. An apparatus includes a register file with a plurality of registers and a plurality of compute units configured to execute wavefronts. A control unit of the apparatus is configured to allow a first number of wavefronts to execute concurrently on the plurality of compute units. The control unit is configured to allow no more than a second number of wavefronts to execute concurrently on the plurality of compute units, wherein the second number is less than the first number, in response to detection that thrashing of the register file is above a threshold. The control unit is configured to detect said thrashing based at least in part on a number of registers in use by executing wavefronts that spill to memory.Type: GrantFiled: December 29, 2020Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Bradford Michael Beckmann, Steven Tony Tye, Brian L. Sumner, Nicolai Hähnle
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Patent number: 11876718Abstract: Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.Type: GrantFiled: October 6, 2022Date of Patent: January 16, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Narendra Kamat
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Patent number: 11875425Abstract: Implementing heterogeneous wavefronts on a graphics processing unit (GPU) is disclosed. A scheduler assigns heterogeneous wavefronts for execution on a compute unit of a processing device. The heterogeneous wavefronts include different types of wavefronts such as vector compute wavefronts and service-level wavefronts that vary in resource requirements and instruction sets. As one example, heterogeneous wavefronts may include scalar wavefronts and vector compute wavefronts that execute on scalar units and vector units, respectively. Distinct sets of instructions are executed for the heterogeneous wavefronts on the compute unit. Heterogeneous wavefronts are processed in the same pipeline of the processing device.Type: GrantFiled: December 28, 2020Date of Patent: January 16, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sooraj Puthoor, Bradford Beckmann, Nuwan Jayasena, Anthony Gutierrez
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Patent number: 11874774Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.Type: GrantFiled: September 24, 2020Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Ravindra N. Bhargava, Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam
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Patent number: 11875875Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.Type: GrantFiled: December 29, 2021Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
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Patent number: 11874739Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.Type: GrantFiled: September 25, 2020Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas Sridharan, Shaizeen Aga, Nuwan Jayasena, Michael Ignatowski, Shrikanth Ganapathy, John Kalamatianos
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Patent number: 11869874Abstract: A stacked die system includes at least three dies. A first die has a same design as a second die. The first die includes a first circuit, and the second die includes a corresponding second circuit. A signal is received at the first die and sent to the third die via the second die. The signal is routed through either the first circuit or the second circuit but not both. Accordingly, an operation is performed on the signal prior to the signal reaching the third die but the operation is not performed by both the first circuit and the second circuit.Type: GrantFiled: December 14, 2020Date of Patent: January 9, 2024Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, David Johnson
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Patent number: 11868306Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.Type: GrantFiled: September 13, 2022Date of Patent: January 9, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Michael L. Chu, Ashwin Aji, Muhammad Amber Hassaan
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Patent number: 11869140Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.Type: GrantFiled: April 19, 2021Date of Patent: January 9, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Mangesh P. Nijasure, Randy W. Ramsey, Todd Martin
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Patent number: 11868818Abstract: Techniques for selectively executing a lock instruction speculatively or non-speculatively based on lock address prediction and/or temporal lock prediction. including methods an devices for locking an entry in a memory device. In some techniques, a lock instruction executed by a thread for a particular memory entry of a memory device is detected. Whether contention occurred for the particular memory entry during an earlier speculative lock is detected on a condition that the lock instruction comprises a speculative lock instruction. The lock is executed non-speculatively if contention occurred for the particular memory entry during an earlier speculative lock. The lock is executed speculatively if contention did not occur for the particular memory entry during an earlier speculative lock.Type: GrantFiled: September 22, 2016Date of Patent: January 9, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Gregory W. Smaus, John M. King, Matthew A. Rafacz, Matthew M. Crum
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Patent number: 11868759Abstract: Shader source code performance prediction is described. In accordance with the described techniques, an update to shader source code for implementing a shader is received. A prediction of performance of the shader on a processing unit is generated based on the update to the shader source code. Feedback about the update is output. The feedback includes the prediction of performance of the shader. In one or more implementations, generating the prediction of performance of the shader includes compiling the shader source code with the update to generate a representation of the shader, inputting the representation of the shader to one or more machine learning models, and receiving the prediction of performance of the shader as an output from the one or more machine learning models.Type: GrantFiled: December 8, 2021Date of Patent: January 9, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Amit Ben-Moshe, Ian Charles Colbert
