Patents Assigned to Advanced Micro Devices
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Patent number: 11709681Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.Type: GrantFiled: December 11, 2017Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jay Fleischman, Michael Estlick, Michael Christopher Sedmak, Erik Swanson, Sneha V. Desai
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Patent number: 11710698Abstract: A layout for a 6T SRAM cell array is disclosed. The layout doubles the number of bits per bit cell in the array by implementing dual pairs of bitlines spanning bit cell columns in the array. Alternating connections (e.g., alternating vias) may be provided for wordline access to the bitlines in the layout. Alternating the connections may reduce RC delay in the layout.Type: GrantFiled: September 24, 2020Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: John J. Wuu, Richard T. Schultz
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Patent number: 11709327Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.Type: GrantFiled: June 28, 2021Date of Patent: July 25, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Brett P. Wilkerson, Raja Swaminathan, Kong Toon Ng, Rahul Agarwal
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Patent number: 11710207Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.Type: GrantFiled: March 30, 2021Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Christopher J. Brennan, Nishank Pathak
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Patent number: 11709745Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.Type: GrantFiled: January 31, 2022Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Michael Ignatowski, Vilas Sridharan
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Patent number: 11709670Abstract: An electronic device includes a processor and a storage device having a file system with a plurality of directories. The processor executes an application that has a dependency on a shared library, the shared library having a dependency on a runtime component. When executing the application, the processor loads the shared library, the loading including executing a constructor for the shared library. Executing the constructor causes the processor to identify a selected directory where a compatible version of the runtime component is to be found based on a location of the shared library in the file system, the location of the shared library being determined from an application context from the application. When subsequently loading the runtime component for execution, the processor locates the runtime component in the selected directory.Type: GrantFiled: April 14, 2020Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Srinivasan Subramanian, Pruthvi K. Madugundu, Freddy Paul, Jagadish Krishnamoorthy, Diwakar Das, Praveen K. Jain
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Patent number: 11711571Abstract: A server offloads graphics effects processing to a client device with graphics processing resources by determining a modification to a graphics effects operation, generating a portion of a rendered video stream using the modification to the graphics effects operation, and providing an encoded representation of the portion of the rendered video stream to the client device, along with metadata representing the modification implemented. The client device decodes the encoded representation to recover the portion of the rendered video stream and selectively performs a graphics effects operation on the recovered portion to at least partially revert the resulting graphics effects for the portion to the intended effects without the modification implemented by the server.Type: GrantFiled: March 5, 2021Date of Patent: July 25, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Ihab Amer, Guennadi Riguer, Thomas Perry, Mehdi Saeedi, Gabor Sines, Yang Liu
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Patent number: 11709536Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.Type: GrantFiled: September 23, 2020Date of Patent: July 25, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Greg Sadowski, Sriram Sundaram, Stephen Kushnir, William C. Brantley, Michael J. Schulte
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Patent number: 11706415Abstract: Still frame detection for single pass video data, including: determining that an average quantization parameter of a frame of video data falls below a quantization parameter threshold; determining whether an amount of skipped macroblocks in the frame meets a skipped macroblock threshold; and responsive to the amount of skipped macroblocks exceeding the skipped macroblock threshold, identifying the frame as a still frame.Type: GrantFiled: December 28, 2020Date of Patent: July 18, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Mehdi Semsarzadeh, Jiao Wang, Yao Wen Yu, Edward Harold, Richard E. George
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Patent number: 11703932Abstract: A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.Type: GrantFiled: June 24, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Amit P. Apte
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Patent number: 11704250Abstract: Systems and methods are disclosed for maintaining insertion policies of a lower-level cache. Techniques are described for selecting, based on metadata of an evicted data block received from an upper-level cache, an insertion policy out of the insertion policies. Then, determining, based on the selected insertion policy, whether to insert the data block into the lower-level cache. If it is determined to insert, the data block is inserted into the lower-level cache according to the selected insertion policy. Techniques for dynamically updating the insertion policies of the lower-level cache are also disclosed.Type: GrantFiled: September 28, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Paul J. Moyer
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Patent number: 11704183Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.Type: GrantFiled: December 7, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Kedarnath Balakrishnan, James R. Magro, Kevin Michael Lepak, Vilas Sridharan
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Patent number: 11706385Abstract: Machine learning-based multi-view video conferencing from single view video data, including: identifying, in video data, a plurality of objects; and generating a user interface comprising a plurality of first user interface elements each comprising a portion of the video data corresponding to one or more of the plurality of objects.Type: GrantFiled: September 30, 2021Date of Patent: July 18, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Roto Le
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Patent number: 11703937Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.Type: GrantFiled: September 23, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Patent number: 11704198Abstract: A method and apparatus provide recovery from a computing device boot up error by detecting a current boot up error in the computing device, loading a plurality of recovery pre-EFI initialization modules (PEIMs), of a recovery unified extensible firmware interface (UEFI) BIOS for execution, wherein the recovery PEIMS include executable code to pre-initialize at least a processing unit and memory of the computing device in a pre-EFI initialization (PEI) phase of a multi-phase platform initialization operation, and recovering from the boot up error by booting up the computing device using the loaded plurality of recovery pre-EFI initialization modules.Type: GrantFiled: March 29, 2021Date of Patent: July 18, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Mohammad Younas Khan Pathan
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Patent number: 11704277Abstract: Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.Type: GrantFiled: December 16, 2019Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Majed Valad Beigi, Yasuko Eckert, Dongping Zhang
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Patent number: 11704248Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.Type: GrantFiled: November 6, 2020Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: William L. Walker, Michael L. Golden, Marius Evers
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Patent number: 11703930Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: GrantFiled: July 21, 2021Date of Patent: July 18, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Patent number: 11700004Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.Type: GrantFiled: January 28, 2022Date of Patent: July 11, 2023Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.Inventor: HaiFeng Zhou
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Publication number: 20230214345Abstract: A device in an interconnect network is provided. The device comprises an end point processor comprising end point memory and an interconnect network link in communication with an interconnect network switch. The device is configured to issue, by the end point processor, a request to send data from the end point memory to other end point memory of another end point processor of another device in the interconnect network and provide, to the interconnect network switch, the request using memory addresses from a global memory address map which comprises a first global memory address range for the end point processor and a second global memory address range for the other end point processor.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Micro Devices, Inc.Inventor: Brock A. Taylor
