Patents Assigned to Advanced Micro Devices
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Patent number: 11636054Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.Type: GrantFiled: March 31, 2021Date of Patent: April 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Kevin M. Brandl, Indrani Paul, Jean J. Chittilappilly, Abhishek Kumar Verma, James R. Magro, Kavyashree Pilar
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Patent number: 11636038Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.Type: GrantFiled: January 13, 2022Date of Patent: April 25, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventor: David A. Roberts
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Patent number: 11631187Abstract: Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.Type: GrantFiled: September 24, 2020Date of Patent: April 18, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jan Henrik Achrenius, Mika Tuomi, Kiia Kallio, Pazhani Pillai, Laurent Lefebvre
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Patent number: 11630667Abstract: A processor includes a plurality of vector sub-processors (VSPs) and a plurality of memory banks dedicated to respective VSPs. A first memory bank corresponding to a first VSP includes a first plurality of high vector general purpose register (VGPR) banks and a first plurality of low VGPR banks corresponding to the first plurality of high VGPR banks. The first memory bank further includes a plurality of operand gathering components that store operands from respective high VGPR banks and low VGPR banks. The operand gathering components are assigned to individual threads while the threads are executed by the first VSP.Type: GrantFiled: November 27, 2019Date of Patent: April 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jiasheng Chen, Bin He, Jian Huang, Michael Mantor
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Patent number: 11631624Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a package substrate that has a first edge and a second edge opposite to the first edge. A semiconductor chip is mounted on the package substrate. A thermal interface material is positioned on the semiconductor chip. A lid is positioned over the thermal interface material. A spring biasing mechanism is included that is operable to bias the lid away from the package substrate so that the lid, when subjected to a compressive force, can translate toward the package substrate and impart a compressive force on the thermal interface material.Type: GrantFiled: December 11, 2018Date of Patent: April 18, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Kaushik Mysore Srinivasa Setty, William J. Maxwell
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Patent number: 11630994Abstract: A method of training a neural network includes, at a local computing node, receiving remote parameters from a set of one or more remote computing nodes, initiating execution of a forward pass in a local neural network in the local computing node to determine a final output based on the remote parameters, initiating execution of a backward pass in the local neural network to determine updated parameters for the local neural network, and prior to completion of the backward pass, transmitting a subset of the updated parameters to the set of remote computing nodes.Type: GrantFiled: February 17, 2018Date of Patent: April 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Khaled Hamidouche, Michael W LeBeane, Walter B Benton, Michael L Chu
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Patent number: 11630772Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.Type: GrantFiled: September 29, 2021Date of Patent: April 18, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Paul J. Moyer
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Patent number: 11630502Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.Type: GrantFiled: July 30, 2021Date of Patent: April 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: John P. Petry, Alexander J. Branover, Benjamin Tsien, Christopher T. Weaver, Stephen V. Kosonocky, Indrani Paul, Thomas J. Gibney, Mihir Shaileshbhai Doctor
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Patent number: 11630161Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.Type: GrantFiled: November 8, 2021Date of Patent: April 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Miguel Rodriguez, Stephen Victor Kosonocky, Kaushik Mazumdar
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Patent number: 11630715Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.Type: GrantFiled: December 22, 2020Date of Patent: April 18, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Philip Ng, Buheng Xu
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Patent number: 11625807Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.Type: GrantFiled: February 22, 2021Date of Patent: April 11, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jiasheng Chen, Timour Paltashev, Alexander Lyashevsky, Carl Kittredge Wakeland, Michael J. Mantor
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Patent number: 11625249Abstract: Preserving memory ordering between offloaded instructions and non-offloaded instructions is disclosed. An offload instruction for an operation to be offloaded is processed and a lock is placed on a memory address associated with the offload instruction. In response to completing a cache operation targeting the memory address, the lock on the memory address is removed. For multithreaded applications, upon determining that a plurality of processor cores have each begun executing a sequence of offload instructions, the execution of non-offload instructions that are younger than any of the offload instructions is restricted. In response to determining that each processor core has completed executing its sequence of offload instructions, the restriction is removed. The remote device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.Type: GrantFiled: December 29, 2020Date of Patent: April 11, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jagadish B. Kotra, John Kalamatianos
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Patent number: 11625251Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.Type: GrantFiled: December 23, 2021Date of Patent: April 11, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Varun Agrawal, Yasuko Eckert
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Patent number: 11625352Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.Type: GrantFiled: June 12, 2020Date of Patent: April 11, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava, Raghava Sravan Adidamu
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Patent number: 11626874Abstract: Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.Type: GrantFiled: October 15, 2021Date of Patent: April 11, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Achal Kathuria, Pradeep Jayaraman
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Publication number: 20230109344Abstract: Techniques for performing cache operations are provided. The techniques include tracking performance events for a plurality of test sets of a cache, detecting a replacement policy change trigger event associated with a test set of the plurality of test sets, and in response to the replacement policy change trigger event, operating non-test sets of the cache according to a replacement policy associated with the test set.Type: ApplicationFiled: September 30, 2021Publication date: April 6, 2023Applicant: Advanced Micro Devices, Inc.Inventors: John Kelley, Vanchinathan Venkataramani, Paul J. Moyer
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Publication number: 20230108964Abstract: Methods, devices, and systems for retrieving information based on cache miss prediction. A prediction that a cache lookup for the information will miss a cache is made based on a history table. The cache lookup for the information is performed based on the request. A main memory fetch for the information is begun before the cache lookup completes, based on the prediction that the cache lookup for the information will miss the cache. In some implementations, the prediction includes comparing a first set of bits stored in the history table with a second set of bits stored in the history table. In some implementations, the prediction includes comparing at least a portion of an address of the request for the information with a set of bits in the history table.Type: ApplicationFiled: September 30, 2021Publication date: April 6, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Ciji Isen, Paul J. Moyer
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Publication number: 20230105709Abstract: A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.Type: ApplicationFiled: December 28, 2021Publication date: April 6, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Girish Balaiah Aswathaiya
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Patent number: 11620525Abstract: A heterogeneous processing system includes at least one central processing unit (CPU) core and at least one graphics processing unit (GPU) core. The heterogeneous processing system is configured to compute an activation for each one of a plurality of neurons for a first network layer of a neural network. The heterogeneous processing system randomly drops a first subset of the plurality of neurons for the first network layer and keeps a second subset of the plurality of neurons for the first network layer. Activation for each one of the second subset of the plurality of neurons is forwarded to the CPU core and coalesced to generate a set of coalesced activation sub-matrices.Type: GrantFiled: September 25, 2018Date of Patent: April 4, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Abhinav Vishnu
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Patent number: 11620224Abstract: Techniques for controlling prefetching of instructions into an instruction cache are provided. The techniques include tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the tracking, and adjusting prefetch activity based on the throttle toggle.Type: GrantFiled: December 10, 2019Date of Patent: April 4, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Aparna Thyagarajan, Ashok Tirupathy Venkatachar, Marius Evers, Angelo Wong, William E. Jones
