Patents Assigned to Advanced Micro Devices
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Patent number: 11915337Abstract: Systems, apparatuses, and methods for implementing a downsampler in a single compute shader pass are disclosed. A central processing unit (CPU) issues a single-pass compute shader kernel to perform downsampling of a texture on a graphics processing unit (GPU). The GPU includes a plurality of compute units for executing thread groups of the kernel. Each thread group fetches a patch of the texture, and each individual thread downsamples four quads of texels to compute mip levels 1 and 2 independently of the other threads. For mip level 3, texel data is written back over one of the local data share (LDS) entries from which the texel data was loaded. This eliminates the need for a barrier between loads and stores for computing mip level 3. The remaining mip levels are computed in a similar fashion by the thread groups of the single-pass kernel.Type: GrantFiled: February 23, 2021Date of Patent: February 27, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Lou Isabelle Kramer, Matthäus G. Chajdas
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Patent number: 11911839Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.Type: GrantFiled: December 28, 2021Date of Patent: February 27, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Rahul Agarwal, Raja Swaminathan, Brett P. Wilkerson
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Patent number: 11917794Abstract: Separating temperature domains in cooled systems, including: cooling at least one first component of a circuit board using a first cooling system; and conductively coupling the at least one first component to at least one second component using a superconductive portion of a power plane of the circuit board.Type: GrantFiled: October 30, 2020Date of Patent: February 27, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Andrew G. Kegel, Jeffrey Bialozor
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Patent number: 11916556Abstract: The disclosed method of operation for a data latch (DLATCH) circuit may include receiving, by an input component of the DLATCH circuit, an input signal. The method may additionally include storing, by a combinatorial gate of the DLATCH circuit, a state of the input signal, wherein the combinatorial gate corresponds to at least one of an AND-OR-inverted (AOI22) cell or an OR-AND-inverted (OAI22) cell. The method may further include providing an output signal, by an output component of the DLATCH circuit, wherein the output signal has the state stored by the combinatorial gate. Various other methods, systems, and circuits are also disclosed.Type: GrantFiled: August 26, 2022Date of Patent: February 27, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Ioan Cordos
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Patent number: 11914517Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.Type: GrantFiled: November 11, 2020Date of Patent: February 27, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sergey Blagodurov, Marko Scrbak, Brandon K. Potter
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Patent number: 11915359Abstract: Systems, apparatuses, and methods for implementing kernel software driven color remapping of rendered primary surfaces are disclosed. A system includes at least a general processor, a graphics processor, and a memory. The general processor executes a user-mode application, a user-mode driver, and a kernel-mode driver. A primary surface is rendered on the graphics processor on behalf of the user-mode application. The primary surface is stored in memory locations allocated for the primary surface by the user-mode driver and the kernel-mode driver is notified when the primary surface is ready to be displayed. Rather than displaying the primary surface, the kernel-mode driver causes the pixels of the primary surface to be remapped on the graphics processor using a selected lookup table (LUT) so as to generate a remapped surface which stored in memory locations allocated for the remapped surface by the user-mode driver. Then, the remapped surface is displayed.Type: GrantFiled: December 12, 2019Date of Patent: February 27, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jason Wen-Tse Wu, Parimalkumar Patel, Jia Hui Li, Chao Zhan
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Patent number: 11908065Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.Type: GrantFiled: June 20, 2022Date of Patent: February 20, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Daniel James Skinner, Michael John Livesley, David William John Pankratz
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Patent number: 11907126Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.Type: GrantFiled: December 9, 2020Date of Patent: February 20, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Robert B. Cohen, Tzu-Wei Lin, Anthony J. Bybell, Sudherssen Kalaiselvan, James Mossman
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Patent number: 11907070Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.Type: GrantFiled: July 30, 2021Date of Patent: February 20, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Eric Busta, Michael L. Golden, Sean M. O′Mullan, James Wingfield, Keith A. Kasprak, Russell Schreiber, Michael Estlick
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Patent number: 11909404Abstract: A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.Type: GrantFiled: December 12, 2022Date of Patent: February 20, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Andy Huei Chu, Karthik Gopalakrishnan, Pradeep Jayaraman
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Publication number: 20240054332Abstract: Methods, devices, systems, and instructions for adaptive quantization in an artificial neural network (ANN) calculate a distribution of ANN information; select a quantization function from a set of quantization functions based on the distribution; apply the quantization function to the ANN information to generate quantized ANN information; load the quantized ANN information into the ANN; and generate an output based on the quantized ANN information. Some examples recalculate the distribution of ANN information and reselect the quantization function from the set of quantization functions based on the resampled distribution if the output does not sufficiently correlate with a known correct output. In some examples, the ANN information includes a set of training data. In some examples, the ANN information includes a plurality of link weights.Type: ApplicationFiled: October 27, 2023Publication date: February 15, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Daniel I. Lowell, Sergey Voronov, Mayank Daga
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Publication number: 20240053891Abstract: Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage solution without reducing the amount of system memory available to an operating system running on the one or more processing units.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Applicant: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Patent number: 11900123Abstract: A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.Type: GrantFiled: December 13, 2019Date of Patent: February 13, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Fuad Ashkar, Manu Rastogi, Harry J. Wise
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Patent number: 11899520Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.Type: GrantFiled: April 26, 2022Date of Patent: February 13, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ashish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
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Patent number: 11902571Abstract: Region of interest (ROI)-based upscaling for video conferences, the method including: identifying, in a video frame of a video conference at a first resolution, a boundary region for an object; applying, to a portion of the video frame bound by the boundary region, a machine learning upscaling algorithm to generate an upscaled portion of the video frame corresponding to a second resolution; and generating an upscaled video frame at the second resolution by combining a first plurality of pixels in the upscaled portion of the video frame corresponding to the object with a second plurality of pixels.Type: GrantFiled: September 28, 2021Date of Patent: February 13, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Roto Le
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Patent number: 11900499Abstract: A technique for executing commands for an accelerated processing device is provided. The technique includes obtaining an iteration number and predication data from metadata for an iterative indirect command buffer; for each iteration indicated by the iteration number, performing commands of the iterative indirect command buffer as specified by the predication data; and ending processing of the iterative indirect command buffer in response to processing a number of iterations equal to the iteration number.Type: GrantFiled: September 22, 2020Date of Patent: February 13, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Anirudh Rajendra Acharya, Ruijin Wu, Alexander Fuad Ashkar, Harry J. Wise
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Patent number: 11902658Abstract: Systems, apparatuses, and methods for implementing an instant auto-focus mechanism with distance estimation are disclosed. A camera includes at least an image sensor, one or more movement and/or orientation sensors, a timer, a lens, and control circuit. The control circuit receives first and second images captured by the image sensor of a given scene. The control circuit calculates a distance between first and second camera locations when the first and second images, respectively, were captured based on the one or more movement and/or orientation sensors and the timer. Next, the control circuit calculates an estimate of a second distance between the camera and an object in the scene based on the distance between camera locations and angles between the camera and the object from the first and second locations. Then, the control circuit causes the lens to be adjusted to bring the object into focus for subsequent images.Type: GrantFiled: August 31, 2020Date of Patent: February 13, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Po-Min Wang, Yu-Huai Chen
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Patent number: 11900161Abstract: Memory allocation for processing-in-memory operations, including: receiving, by an allocation module, a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; determining a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern interleaves a plurality of component pages of a memory page across the plurality of data structure operands; and allocating the memory page based on the determined memory allocation pattern.Type: GrantFiled: March 24, 2020Date of Patent: February 13, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Anirban Nag, Nuwan Jayasena, Shaizeen Aga
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Patent number: 11899642Abstract: A method and apparatus perform a first hash operation on a first key wherein the first hash operation is biased to map the first key and associated value to a set of frequently-accessed buckets in a hash table. An entry for the first key and associated value is stored in the set of frequently-accessed buckets. A second hash operation is performed on a second key wherein the second hash operation is biased to map the second key and associated value to a set of less frequently-accessed buckets in the hash table. An entry for the second key and associated value is stored in the set of less frequently-accessed buckets. The method and apparatus perform a hash table look up of the requested key in the set of frequently-accessed buckets, if the requested key is not found, then a hash table lookup is performed in the set of less frequently-accessed buckets.Type: GrantFiled: December 17, 2019Date of Patent: February 13, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Nuwan Jayasena
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Publication number: 20240045718Abstract: Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup dependency instruction including an indication to prioritize execution of the third workgroup has been executed.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Alexandru Dutu, Marcus Nathaniel Chow, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood