Patents Assigned to Advanced Micro Devices
  • Patent number: 11140368
    Abstract: Systems, apparatuses, and methods for scheduling beamforming training during vertical blanking intervals (VBIs) are disclosed. A system includes a transmitter sending a video stream over a wireless link to a receiver. The wireless link between the transmitter and the receiver has capacity characteristics that fluctuate with variations in the environment. To combat the fluctuating capacity characteristics of the link, the transmitter and the receiver perform periodic beamforming training procedures to determine whether to adjust the beamforming characteristics of their respective antennas. To avoid interfering with the video data being sent, the system waits until a VBI to perform a beamforming training procedure. If the beamforming training procedure cannot be completed in a single VBI, then multiple VBIs can be used for performing separate portions of the beamforming training procedure. In one embodiment, the system can perform a beamforming training procedure every N VBIs, where N is a positive integer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 5, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ngoc Vinh Vu, David Robert Stark, Jr., Carson Ryley Reece Green
  • Patent number: 11137941
    Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 5, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, James R. Magro, Kedarnath Balakrishnan
  • Patent number: 11140107
    Abstract: Various messaging systems and methods are disclosed for meeting invitation management. In one aspect, a method of messaging is provided that includes generating a message to invite one or more invitees to a meeting. The message includes an assertion to suppress an auto-responder of the one or more invitees. The message is sent to the one or more invitees. The assertion suppresses the auto-responder of the one or more invitees.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 5, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Andrew G. Kegel, Arkaprava Basu
  • Patent number: 11138015
    Abstract: A compute unit includes single-instruction-multiple-data (SIMD) lanes that implement a pipeline. The compute unit also includes a scheduler to schedule the SIMD lanes to apply a binary associative operation to pairs of elements associated with ordered sets of elements. Subsets of the SIMD lanes concurrently apply the binary associative operation to pairs of elements at different levels of upsweep trees associated with the ordered sets of elements. Application of the binary associative operation is used to perform a reduction operation or a scan operation on the ordered sets of elements. In the case of a scan operation, the scheduler schedules the SIMD lanes to concurrently apply the binary associative operation to pairs of elements at different levels of downsweep trees associated with the ordered sets of elements subsequent to applying the binary associative operation at different levels of the upsweep trees.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Alexander Dodd Breslow
  • Publication number: 20210303987
    Abstract: A technique for performing neural network operations is disclosed. The technique includes identifying a first matrix tile and a second matrix tile, obtaining first range information for the first matrix tile and second range information for the second matrix tile, selecting a matrix multiplication path based on the first range information and the second range information, and performing a matrix multiplication on the first matrix tile and the second matrix tile using the selected matrix multiplication path to generate a tile matrix multiplication product.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Maxim V. Kazakov, Samuel Lawrence Wasmundt
  • Publication number: 20210304488
    Abstract: Devices, systems, and methods for sampling partially resident texture data. An instruction which includes a residency map descriptor is received. The instruction is executed to retrieve partially resident texture data from a mipmap stored in a memory based on the residency map descriptor. The residency map descriptor includes a residency map.
    Type: Application
    Filed: October 29, 2020
    Publication date: September 30, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Fataneh F. Ghodrat, Michael Lee Grossfeld, Kevin Warren Furrow
  • Publication number: 20210304486
    Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
  • Publication number: 20210304349
    Abstract: A technique for executing commands for an accelerated processing device is provided. The technique includes obtaining an iteration number and predication data from metadata for an iterative indirect command buffer; for each iteration indicated by the iteration number, performing commands of the iterative indirect command buffer as specified by the predication data; and ending processing of the iterative indirect command buffer in response to processing a number of iterations equal to the iteration number.
    Type: Application
    Filed: September 22, 2020
    Publication date: September 30, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anirudh Rajendra Acharya, Ruijin Wu, Alexander Fuad Ashkar, Harry J. Wise
  • Publication number: 20210304484
    Abstract: A technique for performing ray tracing operations is provided. The technique includes receiving a ray for an intersection test, testing the ray against boxes specified in a bounding volume hierarchy to eliminate one or more boxes or triangles from consideration, unpacking a triangle from a compressed triangle block of the bounding volume hierarchy, the compressed triangle block including two or more triangles that share at least one vertex, and testing the ray for intersection against at least one of the unpacked triangles.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Young In Yeo
  • Patent number: 11132327
    Abstract: A method and apparatus for physical layer bypass data transmission between physical coding sub-layers (PCS) includes encoding the data for transmission over a serial low-speed link. The data is transmitted from a first PCS via a serial connection over a serializer/deserializer (SERDES) transmission bypass path The data is received by a second PCS via a SERDES receive bypass path.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 28, 2021
    Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Tresidder, Yanfeng Wang, Shiqi Sun
  • Patent number: 11132300
    Abstract: A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: September 28, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gabriel H. Loh, James M. O'Connor
  • Patent number: 11132204
    Abstract: A processing system includes a set of queues to store command buffers prior to execution in a corresponding plurality of pipelines. The processing system also includes one or more first doorbells and a second doorbell. The first doorbells map to one or more queues in the set of queues on a one-to-one basis. The second doorbell maps to a subset of the set of queues on a one-to-many basis. A doorbell monitor generates an interrupt in response to an empty queue in the subset becoming a non-empty queue. A scheduler polls the subset in response to the interrupt. The scheduler schedules a command buffer from the non-empty queue for execution or adds the command buffer to a pool for subsequent execution.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 28, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Rex Eldon McCrary
  • Patent number: 11125815
    Abstract: A reconfigurable optic probe is used to measure signals from a device under test. The reconfigurable optic probe is positioned at a target probe location within a cell of the device under test. The cell including a target net to be measured and non-target nets. A test pattern is applied to the cell and a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: i) configuring the reconfigurable optic probe to produce a ring-shaped beam having a relatively low-intensity region central to the ring-shaped beam; (ii) re-applying the test pattern to the cell at the target probe location with the relatively low-intensity region applied to the target net and obtaining a cross-talk LP waveform in response; (iii) normalizing the cross-talk LP waveform; and (iv) determining a target net waveform by subtracting the normalized cross-talk LP waveform from the LP waveform.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 21, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Venkat Krishnan Ravikumar, Jiann Min Chin, Joel Yang Kwang Wei, Pey Kin Leong
  • Publication number: 20210287421
    Abstract: A technique for performing a ray tracing operation for a ray is provided. The method includes performing one or more ray-box intersection tests for the ray against one or more bounding boxes of a bounding volume hierarchy to eliminate one or more nodes of the bounding volume hierarchy from consideration, for one or more triangles of the bounding volume hierarchy that are not eliminated by the one or more ray-box intersection tests, performing one or more ray-triangle intersection tests utilizing samples displaced from a centroid position of the ray, and invoking one or more shaders of a ray tracing pipeline for the samples based on results of the ray-triangle intersection tests.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Chen Huang
  • Publication number: 20210287422
    Abstract: Techniques for performing ray tracing for a ray are provided. The techniques include, based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident, obtaining a first portion of the bounding volume hierarchy associated with the first memory page, traversing the first portion of the bounding volume hierarchy according to a ray intersection test, based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident, and in response to the second memory page being classified as valid and non-resident, determining that a miss occurs for each node of the bounding volume hierarchy within the second memory page.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Fataneh Ghodrat
  • Patent number: 11120725
    Abstract: A method and apparatus for gamut mapping color gradient preservation is described. In one example, the method and apparatus obtains a source image having a plurality of source color gamut pixels in a source color gamut, wherein the plurality of source color gamut pixels include a same hue value and a same luminance value and define a color gradient, and converts the plurality of source color gamut pixels to a plurality of target color gamut pixels such that the color gradient of the plurality of source color gamut pixels is preserved by the plurality of target color gamut pixels in a target color gamut. The method and apparatus provides the plurality of target color gamut pixels for display on a target color gamut display.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Essam Aly
  • Patent number: 11120190
    Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to power and ground posts in metal zero of a neighboring cell by abutment. The place-and-route tool doesn't need to perform a further routing step after placing the cells. For other variations, the power and ground posts are not routed to the boundary edge and the place-and-route tool routes power and ground connections in metal zero between the standard cell and the neighbor cell.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 11119893
    Abstract: Various computing systems and methods of using the same are disclosed. In one aspect, a computing system is provided that includes a semiconductor chip that is operable to execute start up self test code. An encoder is operable to encode the progress of the execution of the start up self test code to generate encoded debug code. Also included is means for wirelessly outputting the encoded debug code from the computing system.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 14, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Shiqun Xie, Donald L. Cheung
  • Patent number: 11119944
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 14, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 11119665
    Abstract: A processing system scales power to memory and memory channels based on identifying causes of stalls of threads of a wavefront. If the cause is other than an outstanding memory request, the processing system throttles power to the memory to save power. If the stall is due to memory stalls for a subset of the memory channels servicing memory access requests for threads of a wavefront, the processing system adjusts power of the memory channels servicing memory access request for the wavefront based on the subset. By boosting power to the subset of channels, the processing system enables the wavefront to complete processing more quickly, resulting in increased processing speed. Conversely, by throttling power to the remainder of channels, the processing system saves power without affecting processing speed.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 14, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Shomit N. Das, Kishore Punniyamurthy