Patents Assigned to Advanced Micro Devices
  • FLEXIBLE MULTI-USER GRAPHICS ARCHITECTURE
    Publication number: 20210089423
    Abstract: A technique for operating a processor that includes multiple cores is provided. The technique includes determining a number of active applications, selecting a processor configuration for the processor based on the number of active applications, configuring the processor according to the selected processor configuration, and executing the active applications with the configured processor.
    Type: Application
    Filed: June 26, 2020
    Publication date: March 25, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Vineet Goel
  • Method and apparatus for managing power in a thermal couple aware system
    Patent number: 10955884
    Abstract: A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. If the evaluated candidate configuration mapping provides a better metric than the stored configuration, the stored configuration is updated with the evaluated candidate configuration mapping, and programming instructions are executed in accordance with the candidate configuration mapping if no other configuration mappings are to be determined.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei Huang, Manish Arora, Abhinandan Majumdar, Indrani Paul, Leonardo de Paula Rosa Piga
  • Retaining cache entries of a processor core during a powered-down state
    Patent number: 10956332
    Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: William L. Walker, Michael L. Golden, Marius Evers
  • Transition into and out of a partially-off power state
    Patent number: 10955892
    Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jyoti Raheja, Alexander J. Branover
  • Memory system with region-specific memory access scheduling
    Patent number: 10956044
    Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Yi Xu, Nuwan S. Jayasena, Yuan Xie
  • Back side metallization
    Patent number: 10957669
    Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas P. Dolbear, Daniel Cavasin, Sanjay Dandia
  • Saving power in the command processor using queue based watermarks
    Patent number: 10955901
    Abstract: Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander Fuad Ashkar, Angel E. Socarras, Rex Eldon McCrary
  • Hybrid render with preferred primitive batch binning and sorting
    Patent number: 10957094
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 23, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
  • Device and method for accelerating matrix multiply operations
    Patent number: 10956536
    Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
  • Virtual reality beamforming
    Patent number: 10959111
    Abstract: Systems, apparatuses, and methods for implementing enhanced beamforming training procedures are disclosed. A system includes a transmitter communicating over a wireless link with a receiver. To maintain a high quality of transmission over the wireless link, the transmitter and receiver perform periodic beamforming training procedures to test the various sectors of the transmit and receive antennas. In a wide sector sweep procedure, the transmitter and receiver test wide sectors to find the best wide transmit and receive sectors for transferring data. Then in a narrow sector sweep procedure, narrow sectors within and/or adjacent to the best wide sectors are tested, to find the best narrow sectors. This reduces the amount of sectors that are tested during the enhanced beamforming training procedure by skipping those narrow sectors that are far away from the best wide sectors.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Robert Stark, Jr., John Zhong-Chen Li, Carson Ryley Reece Green, Victor Selvaraj
  • Processor support for hardware transactional memory
    Patent number: 10956163
    Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin Pohlack, Luke Yen
  • System and method for storing cache location information for cache entry transfer
    Patent number: 10956339
    Abstract: A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Paul James Moyer
  • Taint protection during speculative execution
    Patent number: 10956157
    Abstract: A subset of a set of architectural registers in a processing system is marked (or “tainted”) to indicate that speculative use of data in the subset of the architectural registers is constrained based on a taint handling policy. One or more speculation features supported by the processing system are disabled for the instruction so that the one or more speculation features cannot be used on data in the subset. In some cases, values of bits associated with the subset of architectural registers are modified to indicate that the subset is tainted. The taint handling policy can be indicated by values stored in a policy register. Taint markings are tracked in response to values stored in the tainted architectural registers being written to a memory or read from the memory.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David Kaplan, Marius Evers
  • Dynamic memory traffic optimization in multi-client systems
    Patent number: 10949127
    Abstract: Systems, apparatuses, and methods for dynamically optimizing memory traffic in multi-client systems are disclosed. A system includes a plurality of client devices, a memory subsystem, and a communication fabric coupled to the client devices and the memory subsystem. The system includes a first client which generates memory access requests targeting the memory subsystem. Prior to sending a given memory access request to the fabric, the first client analyzes metadata associated with data targeted by the given memory access request. If the metadata indicates the targeted data is the same as or is able to be derived from previously retrieved data, the first client prevents the request from being sent out on the fabric on the data path to memory subsystem. This helps to reduce memory bandwidth consumption and allows the fabric and the memory subsystem to stay in a low-power state for longer periods of time.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Thomas James Gibney
  • Method and apparatus for mitigating row hammer attacks
    Patent number: 10950292
    Abstract: An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor wordline cache, the logic sends a corresponding cache line as a response to the read request, otherwise the logic causes a read of content from the memory. In certain examples, the logic includes a stored bit array and a hash function-based filter, which determines whether any of the candidate upper adjacent address and the candidate lower adjacent address are victim rows represented in the stored bit array.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: SeyedMohammad SeyedzadehDelcheh, Steven Raasch
  • Block level rate control
    Patent number: 10951892
    Abstract: Systems, apparatuses, and methods for performing efficient bitrate control of video compression are disclosed. Logic in a bitrate controller of a video encoder receives a target block bitstream length for a block of pixels of a video frame. When the logic determines a count of previously compressed blocks does not exceed a count threshold, the logic selects a quantization parameter from a full range of available quantization parameters. After encoding the block, the logic determines a parameter based on a first ratio of the achieved block bitstream length to an exponential value of an actual quantization parameter used to generate the achieved block bitstream length. For another block, when the count exceeds the count threshold, the logic generates a quantization parameter based on a ratio of the target block bitstream length to an average of parameters of previously encoded blocks.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Adam H. Li
  • Processor with accelerated lock instruction operation
    Patent number: 10949201
    Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott Thomas Bingham, Marius Evers, Krishnan V. Ramani, Thomas Kunjan
  • Offset correction for pseudo differential signaling
    Patent number: 10944368
    Abstract: Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 9, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milam Paraschou, Jeffrey Cooper
  • Graphics texture footprint discovery
    Patent number: 10943391
    Abstract: Accesses to a mipmap by a shader in a graphics pipeline are monitored. The mipmap is stored in a memory or cache associated with the shader and the mipmap represents a texture at a hierarchy of levels of detail. A footprint in the mipmap of the texture is marked based on the monitored accesses. The footprint indicates, on a per-tile, per-level-of-detail (LOD) basis, tiles of the mipmap that are expected to be accessed in subsequent shader operations. In some cases, the footprint is defined by a plurality of footprint indicators that indicate whether the tiles of the mipmap are expected to be accessed in subsequent shader operations. In that case, the plurality of footprint indicators are set to a first value to indicate that the tile was not access during the first frame or a second value to indicate that the tile was accessed during the first frame.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 9, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Christopher J. Brennan
  • Entropy agnostic data encoding and decoding
    Patent number: 10944422
    Abstract: Entropy agnostic data encoding includes: receiving, by an encoder, input data including a bit string; generating a plurality of candidate codewords, including encoding the input data bit string with a plurality of binary vectors, wherein the plurality of binary vectors includes a set of deterministic biased binary vectors and a set of random binary vectors; selecting, in dependence upon a predefined criteria, one of the plurality of candidate codewords; and transmitting the selected candidate codeword to a decoder.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 9, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Seyedmohammad Seyedzadehdelcheh, Shomit N. Das