Patents Assigned to Advanced Micro Devics, Inc.
  • TRAVERSING MULTIPLE REGIONS OF A BOUNDING VOLUME HIERARCHY IN PARALLEL
    Publication number: 20240212259
    Abstract: An implementation comprises traversing a bounding volume hierarchy for each ray of a plurality of rays concurrently using a plurality of execution items. In response to determining that a first execution item of the plurality of execution items is finished traversing the bounding volume hierarchy for a first ray of the plurality rays, the embodiment causes the first execution item to traverse the bounding volume hierarchy for a second ray of the plurality of rays while a second execution item of the plurality of execution items traverses the bounding volume hierarchy for the second ray. And the embodiment comprises initiating side-effects with the first and second execution items in an order indicated by the bounding volume hierarchy.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, Daniel James Skinner, Michael John Livesley
  • System Memory Training with Chipset Attached Memory
    Publication number: 20240211160
    Abstract: System memory training with chipset attached memory is described. In accordance with the described techniques, a request is received to train a system memory of a device. Responsive to the request, contents of the system memory are transferred to a chipset attached memory. The device is operated using the contents from the chipset attached memory. While the device is being operated using the contents from the chipset attached memory, the system memory is dynamically trained. After the training is complete, the contents are transferred back from the chipset attached memory to the trained system memory.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
  • THROUGH-MAGNETIC INDUCTOR
    Publication number: 20240212908
    Abstract: The disclosed inductor includes a magnetic material surrounding a conductive core. The magnetic material and conductive core can be embedded in a substrate. The magnetic material and conductive core can be formed in the substrate, using a magnetic composite material. Various other systems and methods are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: June 27, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Robert Grant Spurney, Alexander Helmut Pfeiffenberger, Sri Ranga Sai Boyapati, Deepak Vasant Kulkarni
  • Memory Verification Using Processing-in-Memory
    Publication number: 20240212777
    Abstract: Memory verification using processing-in-memory is described. In accordance with the described techniques, memory testing logic is loaded into a processing-in-memory component. The processing-in-memory component executes the memory testing logic to test a memory. An indication is output of a detected fault in the memory based on testing the memory.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Robin Conradine Knauerhase
  • Leveraging Processing in Memory Registers as Victim Buffers
    Publication number: 20240211393
    Abstract: In accordance with the described techniques for leveraging processing in memory registers as victim buffers, a computing device includes a memory, a processing in memory component having registers for data storage, and a memory controller having a victim address table that includes at least one address of a row of the memory that is stored in the registers. The memory controller receives a request to access the row of the memory and accesses data of the row from the registers based on the address of the row being included in the victim address table.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jagadish B Kotra, Dong Kai Wang
  • Physical Adjustment to System Memory with Chipset Attached Memory
    Publication number: 20240211416
    Abstract: Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
  • LOOKUP TABLE OPTIMIZATION FOR HIGH SPEED TRANSMIT FEED-FORWARD EQUALIZATION LINK
    Publication number: 20240214246
    Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Pradeep Jayaraman, Karthik Gopalakrishnan, Andrew Egli
  • ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS
    Publication number: 20240211134
    Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez
  • Extended Training for Memory
    Publication number: 20240211142
    Abstract: Extended training for memory is described. In accordance with the described techniques, a training request to train a memory with extended training is received. The extended training corresponds to a longer amount of time than a default training. The extended training of the memory is performed using a set of target memory settings. In one or more implementations, the extended training is performed during a boot up phase of the computing device.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alicia Wen Ju Yurie Leong, Jayesh Hari Joshi, William Robert Alverson, Joshua Taylor Knight, Jerry Anton Ahrens, Amitabh Mehra, Grant Evan Ley
  • PERFORMANCE OF BANK REFRESH
    Publication number: 20240211173
    Abstract: A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • DEVICES, SYSTEMS, AND METHODS FOR INJECTING FABRICATED ERRORS INTO MACHINE CHECK ARCHITECTURES
    Publication number: 20240211362
    Abstract: An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vilas Sridharan, Hanbing Liu, Francisco L. Duran
  • Alleviating interconnect traffic in a disaggregated memory system
    Patent number: 12019904
    Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: June 25, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vamsee Reddy Kommareddy, Seyedmohammad SeyedzadehDelcheh, Sergey Blagodurov
  • Feed forward training of memory interfaces
    Patent number: 12019876
    Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: June 25, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aaron D Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
  • Multi-level cell memory management
    Patent number: 12019879
    Abstract: Multi-level cell memory management techniques are described. In one example, the memory controller is configured to control whether a single-level cell operation or a multi-level cell operation to be used using different mapping schemes. The single-level cell operation, for instance, is usable to store a data word using two states whereas the multi-level cell operation is usable to store the data word by also using an intermediate state. In order to store the data word using two states, the memory controller is configurable to separate the data word across two word lines in the physical memory. In an implementation, use of the different operations and corresponding mapping schemes by the memory controller alternates between adjacent word lines in physical memory.
    Type: Grant
    Filed: September 25, 2022
    Date of Patent: June 25, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventor: SeyedMohammad SeyedzadehDelcheh
  • System and method to reduce power down entry and exit latency
    Patent number: 12019499
    Abstract: A system and method for fast save/restore is disclosed. The system and method include one or more logical units (LUs) residing in independent power domains, one or more digital frequency synthesizers (DFS), each of the one or more DFS associated with one of the one or more LUs, the one or more DFSs configured to lock a system complex frequency and ramp the one or more LUs to system complex frequency, and one or more slave fast save/restore control (FSRC) units, each slave FSRC unit associated with one of the one or more LUs, the one or more slave FSRC units configured to save/restore the FSRC states of the one or more LUs.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: June 25, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mom-Eng Ng, Dilip Kumar Jha
  • NETWORK COLLECTIVE OFFLOAD MESSAGE CHUNKING MANAGEMENT
    Publication number: 20240205133
    Abstract: The disclosed device can perform a collective operation on received datasets, and split the result into chunks in accordance with a chunking scheme. The device can also forward the chunks in accordance with a routing scheme that can direct chunks to appropriate nodes of a collective network. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Josiah I. Clark
  • NETWORK COLLECTIVE OFFLOADING COST MANAGEMENT
    Publication number: 20240205093
    Abstract: The disclosed device includes a collective engine that can select a communication cost model from multiple communication cost models for a collective operation and configure a topology of a collective network for performing the collective operation using the selected communication cost model. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Josiah I. Clark
  • NETWORK COLLECTIVE OFFLOADING ROUTING MANAGEMENT
    Publication number: 20240205092
    Abstract: The disclosed device includes a collective engine that can receive state information from nodes of a collective network. The collective engine can use the state information to initialize a topology of appropriate data routes between the nodes for the collective operation. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Josiah I. Clark
  • INTERSECTABLE INSTANCE NODES FOR RAY TRACING ACCELERATION STRUCTURE NODES
    Publication number: 20240203033
    Abstract: A technique for performing ray tracing operations is provided. The technique includes, in a first iteration of a ray traversal technique, traversing to an instance node of a bounding volume hierarchy; in a second iteration of the ray traversal technique that is subsequent to the first iteration, transforming a ray based on an instance transform of the instance node to generate a transformed ray; and in the second iteration, performing a ray-box intersection test for box node data of the instance node based on the transformed ray.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, David Kirk McAllister, David Ronald Oldcorn, Michael John Livesley, Daniel James Skinner
  • METHOD AND APPARATUS FOR MANAGING MEMORY
    Publication number: 20240201876
    Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 20, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Lu Lu, Anthony Asaro, Yinan Jiang