Abstract: A method for forming a photomask includes providing a transparent substrate and forming an opaque layer over at least a first portion of the transparent substrate. The opaque layer is patterned to define a mask pattern and expose at least a second portion of the transparent substrate. The second portion is etched to define a phase shifting region. The width of the phase shifting region defines a critical dimension. The critical dimension is measured, and the phase shifting region is etched based on the critical dimension to undercut the optically opaque layer. A photomask includes a transparent substrate and a phase shifting region defined in the transparent substrate. The phase shifting region includes sloped sidewalls having a slope of less than about 85°.
Abstract: A method of using scatterometry measurements to determine and control gate electrode profiles is disclosed. In one embodiment, the method comprises providing a library of optical characteristic traces, each of which correspond to a grating structure comprised of a plurality of gate electrode structures having a known profile, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of gate electrode structures having an unknown profile, and illuminating the formed grating structure. The method further comprises measuring light reflected off of the grating structure to generate an optical characteristic trace for the formed grating structure and determining a profile of the gate electrode structures comprising the formed grating structure by correlating the generated optical characteristic trace to an optical characteristic trace from the library.
Abstract: The present invention is directed to a method of forming conductive interconnections in an integrated circuit device. In one embodiment, the method comprises forming a dielectric stack comprised of multiple layers, and determining a thickness ratio of the layers of the stack. The method further comprises determining an etching process to be performed on the dielectric stack to define an opening for a conductive interconnection based upon the determined thickness ration, and performing the determined etch process on the dielectric stack.
Abstract: The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second process layer comprised of an oxidation resistant material above the first process layer. The method continues with the formation of an opening in the first and second process layers and oxidation of the substrate lying within the opening to form a third process layer. Next, a second opening is formed in the third process layer, and a plurality of sidewall spacers are formed in the second opening. The method concludes with the formation of a gate dielectric above the substrate and between the sidewall spacers, the formation of a gate conductor above the gate dielectric, and the formation of a plurality of source and drain regions in the substrate.
Type:
Grant
Filed:
January 5, 1999
Date of Patent:
July 17, 2001
Assignee:
Advanced Micron Devices, Inc.
Inventors:
Mark I. Gardner, H. Jim Fulford, Charles E. May
Abstract: The present invention is directed to a method and apparatus for reducing the thickness of a process layer. The method comprises generating a relatively high velocity gas stream comprised of active ions that will react with the process layer, and moving the wafer relative to the nozzle to effect a reduction in the thickness of the process layer. The apparatus is comprised of a process chamber, means for securing a wafer in the chamber, a nozzle having an exit that is substantially the same width as the diameter of the wafer positioned in the chamber. The apparatus further comprises a means for moving the wafer relative to the nozzle.