Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits.

Abstract: A processing system selectively renders pixels or blocks of pixels of an image and leaves some pixels or blocks of pixels unrendered to conserve resources. The processing system generates a motion vector field to identify regions of an image having moving areas. The processing system uses a rendering processor to identify as regions of interest those units having little to no motion, based on the motion vector field, and a large amount of edge activity, and to minimize the probability of unrendered pixels, or “holes”, in these regions. To avoid noticeable patterns, the rendering processor applies a probability map to determine the possible locations of holes, assigning to each unit a probability indicating the percentage of pixels within the unit that will be holes, and assigning a lower probability to units identified as regions of interest.

Abstract: A method of managing memory in a network of nodes includes identifying memory resources for each of the plurality of nodes connected to the network, storing memory resource information describing the memory resources, and based on the stored memory resource information, allocating a portion of the memory resources for execution of instructions in a workload, where at least a first node of the plurality of nodes is configured to execute the workload using the allocated portion of the memory resources.

Abstract: A computing system includes a set of computing resources and a datastore to store information representing a corresponding idle power consumption metric and a corresponding peak power consumption metric for each computing resource of the set. The computing system further includes a controller coupled to the set of computing resources and the datastore. The controller is to configure the set of computing resources to meet a power budget constraint for the set based on the corresponding idle power consumption metric and the corresponding peak power consumption metric for each computing resource of the set.

Abstract: A processor maintains a minimum setup time for data being transferred between clock domains, including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. Further, the control module maintains the minimum setup time in response to a change in clock frequency at one or both of the clock domains.

Abstract: A method, a device, and a non-transitory computer readable medium for performing external processing on a display device are presented. An application is executed on the display device. Data is sent from the application to an external processor in direct communication with the display device, if the application requires additional processing capabilities than is available on the display device. Data is received from the external processor and the processed data is displayed on the display device.

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

Abstract: A distributed shared-memory system includes several nodes that each have one or more processor cores, caches, local main memory, and a directory. Each node further includes predictors that use historical memory access information to predict future coherence permission requirements and speculatively initiate coherence operations. In one embodiment, predictors are included at processor cores for monitoring a memory access stream (e.g., historical sequence of memory addresses referenced by a processor core) and predicting addresses of future accesses. In another embodiment, predictors are included at the directory of each node for monitoring memory access traffic and coherence-related activities for individual cache lines to predict future demands for particular cache lines. In other embodiments, predictors are included at both the processor cores and directory of each node.

Abstract: A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

Abstract: A technique for source-side memory request network admission control includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. The method may include injecting memory requests by the first node into the network coupled to the memory system. The injecting has the rate of injection. The technique includes adjusting the rate of injection by the first node. The first node adjusts the rate of injection according to an injection policy for the first node and memory request efficiency indicators. The injection policy may be based on an injection rate limit for the first node. The injection policy for the first node may be based on an injection rate limit per memory channel for the first node.

Abstract: A cluster computer server is configured after a system reset or other configuration event. Each node of a fabric of the cluster compute server is employed, for purposes of configuration, as a cell in a cellular automaton, thereby obviating the need for a special configuration network to communicate configuration information from a central management unit. Instead, the nodes communicate configuration information using the same fabric interconnect that is used to communicate messages during normal execution of software services at the nodes.

Abstract: An apparatus comprising at least one antenna for transmission and/or reception of circularly polarized electromagnetic radiation. The antenna includes a radiating element and a single feed line. The single feed line is coupled between the radiating element and a circuit that drives the antenna. The radiating element has a non-symmetrical outer perimeter shape. The radiating element may include an aperture. The antenna may further include a ground element and a supplemental ground feed structure, the supplemental ground feed structure located between the radiating element and the ground element.

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

Abstract: A processing system selects entries for eviction at one cache based at least in part on the validity status of corresponding entries at a different cache. The processing system includes a memory hierarchy having at least two caches, a higher level cache and a lower level cache. The lower level cache monitors which locations of the higher level cache have been indicated as invalid and, when selecting an entry of the lower level cache for eviction to the higher level cache, selects the entry based at least in part on whether the selected cache entry will be stored at an invalid cache line of the higher level cache.

Abstract: An operating point of one or more components in a processing device may be set using a leakage current estimated based on at least one of a rate of temperature overages or a rate of power overages. In some embodiments, a power management controller may be used to set an operating point of one or more components in the processing device based on at least one of a rate of temperature overages or a rate of power overages for the component(s).

Abstract: Systems, apparatuses, and methods for utilizing a programmable memory command sequencer to generate multiple commands from a single memory request. A sequencer receives requests from a host processor and utilizes any of a plurality of programmable routines in response to determining that a given request meets specific criteria. A given programmable routine generates a plurality of memory commands which are then conveyed to a local memory controller and/or one or more remote memory controllers. The host processor programs the sequencer at boot time and updates the sequencer at runtime in response to changing application behavior. In various embodiments, the sequencer generates a variety of error correction routines in response to different requests received from the host processor.

Abstract: Systems, apparatuses, and methods for generating and utilizing sub-pixel sampling patterns on a processor are disclosed. In one embodiment, a processor includes at least multiple execution units and a memory. The processor generates sub-pixel sampling coordinates within each pixel of an image being rendered based on a rotated grid superimposed on the image. The processor also specifies an amount of rotation for the rotated grid. The processor utilizes the sub-pixel sampling coordinates for determining which locations to sample within the image being rendered. The sampling patterns generated based on these techniques enable using more complex and computationally efficient anti-aliasing resolve filters, resulting in higher quality images.

Abstract: A processing system includes a processor that implements registers to define a state of a virtual machine (VM) running on the processor. The processor detects exit conditions of the VM. The processing system also includes a memory element to store contents of the registers in a first data structure that is isolated from a hypervisor of the VM in response to the processor detecting an exit condition. The VM is to selectively expose contents of a subset of the registers to the hypervisor.

Abstract: Techniques for managing message transmission in a large networked computer system that includes multiple individual networked computing systems are disclosed. Message passing among the computing systems include a sending computing device transmitting a message to a receiver computing device and a receiver computing device consuming that message. A build-up of data stored in a buffer at the receiver can reduce performance. In order to reduce the potential performance degradation associated with large amounts of “waiting” data in the buffer, a sending computer system first determines whether the receiver computer system is ready to receive a message and does not transmit the message if the receiver computer system is not ready. To determine whether the receiver computer system is ready to receive a message, the receiver computer system, at the request of the sending computer system, checks a counting filter that stores indications of whether particular messages are ready.

Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.