Patents Assigned to Advanced Micros Devices, Inc.
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Publication number: 20210012203Abstract: Systems, methods, and devices for increasing inference speed of a trained convolutional neural network (CNN). A first computation speed of first filters having a first filter size in a layer of the CNN is determined, and a second computation speed of second filters having a second filter size in the layer of the CNN is determined. The size of at least one of the first filters is changed to the second filter size if the second computation speed is faster than the first computation speed. In some implementations the CNN is retrained, after changing the size of at least one of the first filters to the second filter size, to generate a retrained CNN. The size of a fewer number of the first filters is changed to the second filter size if a key performance indicator loss of the retrained CNN exceeds a threshold.Type: ApplicationFiled: July 10, 2019Publication date: January 14, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Abhinav Vishnu, Prakash Sathyanath Raghavendra, Tamer M. Elsharnouby, Rachida Kebichi, Walid Ali, Jonathan Charles Gallmeier
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Patent number: 10884319Abstract: A system and method for controlling characteristics of collected image data are disclosed. The system and method include performing pre-processing of an image using GPUs, configuring an optic based on the pre-processing, the configuring being designed to account for features of the pre-processed image, acquiring an image using the configured optic, processing the acquired image using GPUs, and determining if the processed acquired image accounts for feature of the pre-processed image, and the determination is affirmative, outputting the image, wherein if the determination is negative repeating the configuring of the optic and re-acquiring the image.Type: GrantFiled: October 23, 2017Date of Patent: January 5, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Allen H. Rush, Hui Zhou
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Patent number: 10884477Abstract: The described embodiments include a computing device with a plurality of clients and a shared resource for processing job items. During operation, a given client of the plurality of clients stores first job items in a queue for the given client. When the queue for the given client meets one or more conditions, the given client notifies one or more other clients that the given client is to process job items using the shared resource. The given client then processes the first job items from the queue using the shared resource. Based on being notified, at least one other client that has second job items to be processed using the shared resource, processes the second job items using the shared resource. The given client can transition the shared resource between power states to enable the processing of job items.Type: GrantFiled: October 20, 2016Date of Patent: January 5, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Alexander J. Branover, Benjamin Tsien
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Patent number: 10884751Abstract: Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions.Type: GrantFiled: July 13, 2018Date of Patent: January 5, 2021Assignee: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Jagadish B. Kotra
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Patent number: 10884948Abstract: A device includes an address translation table to, in each node of a set of nodes in the address translation table, store a key value and a hash function identifier, a hash engine coupled with the address translation table to, for each node in the set of nodes, calculate a hash result for the key value by executing a hash function identified by the hash function identifier, and a processing unit coupled with the hash engine to, in response to a request to translate a virtual memory address to a physical memory address, identify a physical memory region corresponding to the virtual memory address based on the calculated hash result for each node in the set of nodes.Type: GrantFiled: May 16, 2019Date of Patent: January 5, 2021Assignee: Advanced Micro Devices, Inc.Inventor: Alexander D. Breslow
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Patent number: 10884940Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.Type: GrantFiled: December 21, 2018Date of Patent: January 5, 2021Assignee: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Shrikanth Ganapathy, Shomit Das, Matthew Tomei
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Publication number: 20200409695Abstract: Described herein are techniques for reducing divergence of control flow in a single-instruction-multiple-data processor. The method includes, at a point of divergent control flow, identifying control flow targets for different execution items, sorting the execution items based on the control flow targets, reorganizing the execution items based on the sorting, and executing after the point of divergent control flow, with the reorganized execution items.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: Advanced Micro Devices, Inc.Inventors: David Ronald Oldcorn, Skyler Jonathon Saleh
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Publication number: 20200409851Abstract: Techniques for generating a model for predicting when different hybrid prefetcher configurations should be used are disclosed. Techniques for using the model to predict when different hybrid prefetcher configurations should be used are also disclosed. The techniques for generating the model include obtaining a set of input data, and generating trees based on the training data. Each tree is associated with a different hybrid prefetcher configuration and the trees output certainty scores for the associated hybrid prefetcher configuration based on hardware feature measurements. To decide on a hybrid prefetcher configuration to use, a prefetcher traverses multiple trees to obtain certainty scores for different hybrid prefetcher configurations and identifies a hybrid prefetcher configuration to used based on a comparison of the certainty scores.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Applicant: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Paul S. Keltcher, Mayank Chhablani, Alok Garg, Furkan Eris
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Publication number: 20200409448Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Xiaojie He, Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming So, Felix Yat-Sum Ho, Biao Zhou
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Publication number: 20200409762Abstract: A method and apparatus for servicing a task in a computer system includes receiving the task and if the task is serviceable without waking the fabric, servicing the task by a first service stage entity. If the task is not serviceable by the first service stage entity, the task is serviced by a first processing unit without waking a second processing unit. If the task is not serviceable by the first processing unit, the task is serviced by the second processing unit.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Elliot H. Mednick, Benjamin Tsien
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Publication number: 20200410330Abstract: A technique for manipulating a generic tensor is provided. The technique includes receiving a first request to perform a first operation on a generic tensor descriptor associated with the generic tensor, responsive to the first request, performing the first operation on the generic tensor descriptor, receiving a second request to perform a second operation on generic tensor raw data associated with the generic tensor, and responsive to the second request, performing the second operation on the generic tensor raw data.Type: ApplicationFiled: January 31, 2020Publication date: December 31, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Chao Liu, Daniel Isamu Lowell, Wen Heng Chung, Jing Zhang
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Publication number: 20200409408Abstract: A method operates a first-in-first-out (FIFO) buffer with a first clock, and operates one of a read pointer or a write pointer of the FIFO buffer with the first clock while operating the other one of the read pointer or write pointer with a second clock. One of a serializer fed from the FIFO buffer output, or a de-serializer feeding the FIFO buffer input, is operated with the second clock. Timing pulses indicate that the pointer operating with the second clock has reached a predetermined point in its cycle. The phase of the second clock is adjusted based on a relationship between the timing pulses and an advance period of the pointer operating with the first clock. The pointer operating with the first clock is reset to achieve a desired value for the relationship. A skew created from adjusting the phase of the second clock is corrected.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Applicant: Advanced Micro Devices, Inc.Inventor: Bhuvanachandran K. Nair
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Patent number: 10877926Abstract: A method and system for partial wavefront merger is described. Vector processing machines employ the partial wavefront merger to merge partial wavefronts into one or more wavefronts. The system includes a partial wavefront manager and unified registers. The partial wavefront manager detects wavefronts in different single-instruction-multiple-data (“SIMD”) units which contain inactive work items and active work items (hereinafter referred to as “partial wavefronts”), moves the partial wavefronts into one or more SIMD unit(s) and merges the partial wavefronts into one or more wavefront(s). The unified register allows each active work item in the one or more merged wavefront(s) to access the previously allocated registers in the originating SIMD units. Consequently, the contents of the unified registers do not have to be copied to the SIMD unit(s) executing the one or merged wavefront(s).Type: GrantFiled: July 23, 2018Date of Patent: December 29, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Yunpeng Zhu, Jimshed Mirza
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Patent number: 10880587Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.Type: GrantFiled: September 5, 2019Date of Patent: December 29, 2020Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Lei Zhang, Gabor Sines, Khaled Mammou, David Glen, Layla A. Mah, Rajabali M. Koduri, Bruce Montag
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Patent number: 10872641Abstract: A circuit includes a repeating series of first circuits and a repeating series of second circuits placed next to the repeating series of first circuits and interacts with corresponding portions of the first circuits in the series. The repeating series of second circuits is formed in diffusion regions and diffusion wells which extend along the direction in which the second circuits repeat. The repeating series of the first and second circuits is interrupted by at least one dummy circuit region, which occupies the space of one or more instances of the first and second repeating series. The dummy circuit region also includes taps for biasing the diffusion regions and diffusion wells of the second circuits.Type: GrantFiled: June 27, 2019Date of Patent: December 22, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Russell Schreiber, Keith A. Kasprak
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Patent number: 10871559Abstract: Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio frequency (RF) signals in a first frequency range while operating in the first mode. Additionally, the transmitter operates in a second mode to send video data to the receiver, and the transmitter generates RF signals in the first frequency range while operating in the second mode.Type: GrantFiled: September 29, 2017Date of Patent: December 22, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Ngoc Vinh Vu, Neil Patrick Kelly
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Patent number: 10872047Abstract: A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. Memory interface training between the processor and memory and restoration and initialization of the processor are performed in parallel with each other and with a serial bus controller entering serial bus training to facilitate communication between the processor and a system controller.Type: GrantFiled: July 23, 2018Date of Patent: December 22, 2020Assignee: Advanced Micro Devices, Inc.Inventor: Greg Sadowski
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Patent number: 10873445Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.Type: GrantFiled: December 10, 2019Date of Patent: December 22, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
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Patent number: 10866895Abstract: A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.Type: GrantFiled: December 18, 2018Date of Patent: December 15, 2020Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Philip Ng, Nippon Harshadk Raval, Francisco L. Duran
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Patent number: 10867978Abstract: In at least one embodiment, an integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, and a discrete device disposed laterally with respect to the integrated circuit die and disposed above the redistribution layer. The integrated circuit product may include encapsulant mechanically coupling the redistribution layer, the integrated circuit die, and the discrete device. The integrated circuit product may include first conductive vias through the redistribution layer and second conductive vias through the redistribution layer. The first conductive vias may be electrically coupled to the integrated circuit die and the second conductive vias being electrically coupled to the discrete device. The discrete device may include a discrete capacitor device made from a ceramic material, electrolytic materials, or electrochemical materials.Type: GrantFiled: December 11, 2018Date of Patent: December 15, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Milind S. Bhagavat, Rahul Agarwal
