Abstract: A circuit for allowing a memory module with an asymmetric addressing scheme to effectively operate with a memory controller which a symmetric address scheme is disclosed. The circuit includes a demultiplexer for receiving at least a last address bit from the memory controller and generating a plurality of control signals and a decoder. The decoder includes a plurality of decoder units. Each of the decoder units includes logic for receiving one of the plurality of control signals, a first strobe signal and a second strobe signal from the memory controller. Each of the decoder units also selectably provides a decoded second strobe signal responsive to the demultiplexer.

Abstract: A circuit is provided that allows for the substitution of a memory module with one type of addressing scheme with a second memory module which has a different type of addressing scheme. Through the use of a row address strobe (RAS) generator and address generator which receives multiple RAS signals, a new RAS signal is generated that is in accordance with the one type of addressing scheme and an address signal is provided which indicates which portion of the memory is to be accessed.

Abstract: A circuit is provided that allows for the substitution of a memory module with one type of addressing scheme with a second memory module which has a different type of addressing scheme. Through the use of a row address strobe (RAS) generator and address generator which receives multiple RAS signals, a new RAS signal is generated that is in accordance with the one type of addressing scheme and an address signal is provided which indicates which portion of the memory is to be accessed.