Patents Assigned to Advanced Processor Architectures, LLC
  • Patent number: 10437316
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 8, 2019
    Assignee: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 10162379
    Abstract: A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: December 25, 2018
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edumund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 9778730
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 3, 2017
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 9645603
    Abstract: A system clock signal is distributed to computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers, include input and output ports on which system clock signals are propagated. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: May 9, 2017
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 9429983
    Abstract: A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 30, 2016
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 9372502
    Abstract: A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 21, 2016
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 9220176
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: December 22, 2015
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 8675371
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: March 18, 2014
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Publication number: 20130314888
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Application
    Filed: February 15, 2013
    Publication date: November 28, 2013
    Applicant: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventor: Advanced Processor Architectures, LLC
  • Patent number: 8555096
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: October 8, 2013
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 8381031
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: February 19, 2013
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 8022526
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: September 20, 2011
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Publication number: 20110035626
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Applicant: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Publication number: 20110035177
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Applicant: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Publication number: 20110032688
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Applicant: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Publication number: 20110035612
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Applicant: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Publication number: 20110032677
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Applicant: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins