Abstract: A data processing apparatus comprising an integrated circuit 2 having a processor core 4 surrounded by a scan chain 10 is described. The processor core 4 can execute program instructions using either a system clock signal MClk or a test clock signal DClk. A clock selecting bit S within the program instructions for test operation indicates which clock is to be used and a clock selecting mechanism 12, 14 selects the indicated clock signal and passes this to the processor core 4. When the system clock MClk is selected execution of the program instruction by the processor core 4 may be coordinated with the operation of connected auxiliary circuits such as a DRAM 6.

Abstract: The present invention provides an apparatus and method for processing data, the apparatus comprising a plurality of asynchronous control circuits, each asynchronous control circuit employing a request-acknowledge control loop to control data flow within that asynchronous control circuit, and being arranged to exchange data signals with at least one other of said plurality of asynchronous control circuits. Further, a first of said asynchronous control circuits includes a halt circuit for blocking a control signal in the control loop of the first asynchronous control circuit, thereby preventing the exchange of data signals with said at least one other of said plurality of asynchronous control circuits so as to cause the control loops of said plurality of asynchronous control circuits to become blocked. The present invention is based on an asynchronous design, which only causes transitions in the circuit in response to a request to carry out useful work.

Abstract: A cache memory circuit 36 is described which has a separate read bus 90 and write bus 98. When a given cache row is selected, then simultaneous read and write operations can take place to different words (W#0, W#1, W#2, W#3) within the cache row using the read bus and the write bus. The cache memory circuit 38 having this configuration is particularly suited for use as a write back cache. When a cache miss occurs causing the need for a cache row to be replaced, then the words are replaced starting with the word to which an attempted access triggered the cache miss and proceeding in ascending address order.

Abstract: A digital signal processing system is described in which a microprocessor unit 2 operating under control of microprocessor program instruction words controls data transfer to and from a data storage device 8 and the supply and fetching of data to and from a digital signal processing unit 4.

Abstract: A digital to analogue converter having a plurality of output stages 46. Each output stage 46 includes a tri-state buffer 54 that outputs an on-signal, an off-signal or a pulse width modulated signal PWM that is selected by a multiplexer 52 that operates under control of a chord decoder 50 that is responsive to exponent bits within the input digital signal value. If a pulse width modulated signal is selected, then its duty cycle is controlled by a pulse width modulated decoder 48 that is responsive to mantissa bits within the input digital signal value. A further output provides a pulse width modulated signal of a predetermined duty cycle that may be used as a reference signal to compensate for variations in the operation of the rest of the digital to analogue circuit.

Abstract: A digital to analogue converter having a plurality of output stages 46. Each output stage 46 includes a tri-state buffer 54 that outputs an on-signal, an off-signal or a pulse width modulated signal PWM that is selected by a multiplexer 52 that operates under control of a chord decoder 50 that is responsive to exponent bits within the input digital signal value. If a pulse width modulated signal is selected, then its duty cycle is controlled by a pulse width modulated decoder 48 that is responsive to mantissa bits within the input digital signal value. A further output provides a pulse width modulated signal of a predetermined duty cycle that may be used as a reference signal to compensate for variations in the operation of the rest of the digital to analogue circuit.

Abstract: Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.

Abstract: An integrated circuit 2 implementing JTAG debugging and analysis functions has an IDCODE Instruction which returns predetermined data characteristic of the integrated circuit, e.g. manufacturer, part number and version. A portion 20 of the serial test scan chain of the integrated circuit 2 is reused to load and then serially output this identifying data. The serial input of the test and debugging system is connected during such IDCODE Instructions to the start of the portion 20 of the serial test scan chain. This enables the identifying data of a plurality of integrated circuits with linked serial test scan chains to successively output their identifying data in one operation.

Abstract: A data memory is described in which data words comprising access control bits and further bits are stored at each memory location 34. When a particular memory location is addressed, then the access control bits stored at that memory location are output to control logic 12, 46 that serves to generate a valid access signal. The valid access signal is fed back to the selected memory location and controls whether the further bits stored at that memory location are output. If access to those further bits is not permitted by the access control bits, then the further bits are not output and power is saved. The control logic is responsive to hardware and software flags in addition to the access control bits. The system is particularly suited for use in conjunction with a cache memory.

Abstract: A microprocessor is described having an arithmetic unit 8 that includes a dedicated hardware divider. The hardware divider is responsive to a plurality of different divide instruction codes to generate respective multi-bit portions of a quotient. Each divide instruction can be early terminated when the partial remainder is detected as being zero. Furthermore, subsequent divide instructions to calculate the remaining bits of the quotient can be skipped in response to a flag (Zflag) set within a current programming status register 28. In the described embodiment, a 32-bit divisor and 64-bit dividend serve to produce a 32-bit quotient and a 32-bit remainder. The generation of the 32-bit quotient takes place in response to four different divide instruction codes each responsible for generating a respective 8-bit portion of the quotient.

Abstract: A data processing system incorporating an arithmetic logic unit 20, 22, 24 having an N-bit data pathway and supporting parallel operation program instruction words in which to independent arithmetic operations are carried out in parallel by the arithmetic logic unit upon (N/2)-bit input operand words. Two sets of condition code flags N, Z, C V, SN, SZ, SC, SV responsive to the separate arithmetic logic operations are provided.

Abstract: A data processing system is described having a central processing unit (CPU) 4, a memory management unit (MMU) 6 and a cache memory 8. The CPU 4 makes cache writes in the same clock cycle that the data is output from the CPU 4. In a following clock cycle, the MMU 6 produces a signal IC indicating whether that storage operation was invalid. If the storage operation was invalid, then a flag associated with a cache storage line storing a plurality of output data words is set to indicate such invalid storage.

Abstract: A data processing system is described utilising two instruction sets. Both instruction sets control processing using full N-bit data pathways within a processor core 2. One instruction set is a 32-bit instruction set and the other is a 16-bit instruction set. Both instruction sets are permanently installed and have associated instruction decoding hardware 30, 36, 38.

Abstract: A primary circuit model using a primary simulator 40' operates in conjunction with a plurality of secondary circuit models 10, 20, 30 using a secondary simulator 100. Only signals external to the secondary circuit models are passed between the primary simulator and the secondary simulator. The primary simulator and the secondary simulator independently increment their simulated time when they are active. The secondary simulator is invoked when a signal to which one of the secondary circuit models is responsive is changed by the primary simulator. The secondary simulator is not exited until no further signal changes are being driven by the secondary circuit models at which stage the last asserted values of signals changed by the secondary circuit models are returned to the primary model.

Abstract: A data processing system employing registers for holding data to be processed is described. The registers are grouped into sets of registers 2. A register selecting instruction word controls selection of a particular ones of the registers from within the sets of registers 2 to be available for data processing. The register selecting instruction word includes control fields for each set of registers, the bits of each control field specifying a register swap within the a respective set of register. The new register to be selected is derived from an exclusive OR operation performed upon a currently selected register identification word and the control field for that set of registers.

Abstract: A data processing system has a CPU linked via a unidirectional read bus and a unidirectional write and address bus to a data memory (e.g., cache, RAM, or disk), in the form of a cache memory. Since the read bus and the write and address bus are only driven in one direction, lost time through reversing the direction of signals travel along a bus is avoided. Read-data words and instruction-data words are transferred from the cache memory to a core of the CPU via the read bus. Instruction-address, read-address, write-address, and write-data words are time division multiplexed on the write and address bus to pass from the core to the cache memory. The system supports burst mode transfer thereby reducing the number of addresses that need to be transferred on the write and address bus thereby releasing bandwidth on this bus for use by write-data words.

Abstract: A cache memory in which the address of a required data item is compared with address data stored in a plurality of tag memory sections, a match indicating that the required data item is stored in a corresponding data memory section, is operable in at least a first and a second mode, whereby:(i) in the first mode, only that one of the data memory sections in which the required data word is stored is enabled for operation once the appropriate data memory section has been identified by an address match with the corresponding tag memory section; and(ii) in the second mode, two or more (and preferably all) of the data memory sections are enabled for operation substantially concurrently with the comparison of the required address and the addresses stored in the tag memory sections, an address match being used to select the output of one of the data memory sections.

Abstract: A CPU architecture is provided having a user mode (User32), a plurality of exception modes (IRQ32 etc) and a system mode (System) entered via one of the exception modes. The system mode re-uses the same set of registers (16) as the user mode and yet has access to a set of privileged resources compared to the standard resources of the user mode. Interrupt of the same type are disabled when the system is already in that exception mode, but are re-enabled when the system is moved into the system mode. Branch instructions may be used in the user and system modes, but not the exception modes.

Abstract: Apparatus and method for data processing includes a common data bus (4) to interconnect a bus master circuit (6) with one or more bus slave circuits (8, 10, 12). The data processing apparatus (2) is configured to support burst mode transfers in which an address word is followed by a sequence of data words relating to addresses following on from that specified by the address word. Such transfers increase the number of data words transmitted per address word that need be specified. The data bus (4) includes an address request signal line (16) by which any of the bus slave circuits (8, 10, 12) may request an address word to be transmitted in the next processing cycle rather than a data word. In this way, the bus master circuit (6) need not be specifically adapted for the bus slaves that are attached to the bus (4), since the bus slaves can themselves indicate to what extent they are able to deal with burst mode transfers.

Abstract: Within a data processing system having two alternative clock signals of different frequencies (fclk, mclk) it is necessary to provide a mechanism for switching between the clock signals. When switching from the fast clock (fclk) to the slow clock (mclk), the system adopts the slow clock from the first falling edge (ffe) after a processing delay (PD) associated with the decision as to whether or not to change clocks. This processing delay can be greater than one half of a cycle of the fast clock. In contrast, when switching from the slow clock to the fast clock, the system adopts the fast clock from the first rising edge (fre) following the processing delay. Thus, a system is provided in which differing strategies for synchronization are adopted depending upon the direction of change of the clock signal.