Patents Assigned to Advanced Semiconductors Engineering, Inc.
  • Sawing method for a semiconductor element with a microelectromechanical system
    Patent number: 7674688
    Abstract: A sawing method for a Micro Electro-Mechanical Systems (MEMS) semiconductor device, wherein a gum material is disposed between a wafer having at least one MEMS and a carrier, and the gum material is disposed around the MEMS. The wafer is sawed according to the position correspondingly above the gum material. Finally, the carrier and the gum material are removed. By disposing the gum material between the carrier and the wafer, the MEMS are protected, and the wafer and the MEMS can avoid the pollution of water and foreign material, so that the yield can be improved. Furthermore, the wafer is sawed from the backside till the gum material without sawing through the gum material, so that the carrier is not sawed. Therefore, the carrier can be reused, such that the cost is reduced.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: March 9, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Min Hsiao
  • METHOD OF FABRICATING MULTI-LAYERED SUBSTRATE AND THE SUBSTRATE THEREOF
    Publication number: 20100055392
    Abstract: The present invention directs to fabrication methods of single-sided or double-sided multi-layered substrate by providing a lamination structure having at least a core structure and first and second laminate structures stacked over both surfaces of the core structure. The core structure functions as the temporary carrier for carrying the first and second laminate structures through the double-sided processing procedures. By way of the fabrication methods, the production yield can be greatly improved without increasing the production costs.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 4, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Yuan-Chang Su, Ming-Chiang Lee, You-Lung Yen
  • STACKED TYPE CHIP PACKAGE STRUCTURE
    Publication number: 20100052186
    Abstract: A stacked type chip package structure employs a substrate having a pseudo-cavity or a keep-out zone at one side or both sides thereof. Through the pattern arrangement of the wiring layer and the solder mask layer, the thickness of the entire stacked type chip package structure is effectively reduced as lower wire loops and a thinner mold-cap can be achieved by mounting the chip within the depressed keep-out zone. In particular, the double-sided chip package structures are suitable for package on package structures adopted by mobile applications.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 4, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Bradford J. Factor
  • WIRE BODNING PACKAGE STRUCTURE
    Publication number: 20100052122
    Abstract: A chip package structure employing a die pad integrated with the ground/voltage pad is provided. The die pad for carrying the chip is split into at least two separate sections for accommodating the ground and the voltage. Due to the design of the die pad, the signal fingers may be extended under the chip to be connected with vias, and thermal/ground vias may be arranged under the die pad for thermal or electrical connections. Through such arrangement, all the fingers are located closer to the die, thus decrease the length of bonding wires and reducing the package dimensions.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 4, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Bernd Karl Appelt
  • CHIP SCALE PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20100052156
    Abstract: A chip scale package (CSP) structure and the packaging process thereof are described. By using a matrix of interlinked heat sink units compatible with the block substrate, the packaging process can be simplified and a plurality of packages units or chip scale packages with enhanced thermal performance can be obtained after singulation.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 4, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Bradford J. Factor
  • Integrated circuit device with embedded passive component by flip-chip connection and method for manufacturing the same
    Patent number: 7670876
    Abstract: An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 2, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Mon-Chin Tsai
  • ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20100044850
    Abstract: An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the central portion and the peripheral portion. The central portion, the peripheral portion, and the connecting portions define at least two hollow regions. The leads are disposed around the die pad. The chip is located within the central portion of the die pad and electrically connected to the leads via a plurality of wires. The molding compound encapsulates the chip, the wires, inner leads and a portion of the carrier.
    Type: Application
    Filed: March 16, 2009
    Publication date: February 25, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Hung Lin, Pao-Huei Chang Chien, Ping-Cheng Hu, Wei-Lun Cheng
  • ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20100044843
    Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection.
    Type: Application
    Filed: April 17, 2009
    Publication date: February 25, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
  • Multi-chip package
    Patent number: 7667303
    Abstract: A multi-chip package including a carrier, a first chip, a second chip and a first conductive layer is provided. The first chip is disposed on the carrier and is electrically connected to the carrier through at least one first wire. The second chip is disposed on the first chip and is electrically connected to the first chip through at least one second wire. The first conductive layer is disposed on the second chip and is electrically connected to the first chip or the second chip through at least one third wire. The first conductive layer is electrically connected to the carrier through the at least one fourth wire.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: February 23, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Hsiung Chen, Jen-Te Tseng
  • Surface mounting method
    Patent number: 7662709
    Abstract: An improved surface mounting method applied in a semiconductor package process is provided, wherein the method comprises the following steps: First a substrate having at least one pad set on one surface of the substrate is provided. Then a mask having at least one opening associated with one of the at least one pad is set on the substrate, wherein each opening is separated into a plurality of sub-openings by a segregator to expose the pad. Subsequently, a printing process is conducted to form a conductive layer on each pad. After removing the mask, a passive device is set on the conductive layer over the pad, and a heating treatment is conducted to fix the passive device on the pad.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: February 16, 2010
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Pai-Chou Liu, Wen-Shin Lin, Sheng-Hong Cheng, Yu-Hsin Lee, Ming-Chia Hsieh, Kuan-Hung Yeh, Chia-Wei Chang, Tsung-Chi Chen
  • Punch type substrate strip
    Patent number: 7663208
    Abstract: A punch type substrate strip includes a plurality of substrate units, a plurality of slots and at least one plating-trace collecting hole. The slots are formed around the substrate units. The plating-trace collecting hole is located outside the substrate units. The substrate strip is provided with a plurality of connecting pads, a plurality of first plating traces and at least one second plating trace. The connecting pads are disposed in each substrate unit, and the first plating traces and the second plating trace are electrically connected to the connecting pads. The first plating traces have a plurality of first broken ends located in the slots. The second plating trace is extended across a region located between the slots, and has a second broken end located in the plating-trace collecting hole. Accordingly, more extensive space for plating traces can be provided.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: February 16, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo Hua Chen, She Hong Cheng
  • CHIP PACKAGE STRUCTURE
    Publication number: 20100032822
    Abstract: A chip package structure including a first substrate, a chip, a second substrate, a plurality of conductive wires, a plurality of solder balls and a molding compound is provided. The chip is disposed on the first substrate. The second substrate disposed on the chip has an upper surface and a lower surface, in which a distance of the lower surface relative to the chip is smaller than that of the upper surface relative to the chip. The upper surface has a ball mounting surface and a wire bonding surface. A distance between the wire bonding surface and the first substrate is smaller than that between the ball mounting surface and the first substrate. The conductive wires connect the wire bonding surface to the first substrate. The solder balls are disposed on the ball mounting surface. The molding compound is disposed on the first substrate.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 11, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: CHEN-KAI LIAO, CHENG-YI WENG, MENG-JEN WANG
  • Semiconductor device package and manufacturing method
    Patent number: 7656047
    Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: February 2, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jun Young Yang, You Ock Joo, You Pil Jung
  • Semiconductor package and method for manufacturing the same
    Patent number: 7656043
    Abstract: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: February 2, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Yao Ting Huang
  • EMBEDDED CHIP SUBSTRATE AND FABRICATION METHOD THEREOF
    Publication number: 20100018761
    Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 28, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: YUNG-HUI WANG, Ying-Te Ou
  • Bumping process and structure thereof
    Patent number: 7651937
    Abstract: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: January 26, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
  • Wafer lever fixture and method for packaging micro-electro-mechanical-system devices
    Patent number: 7651888
    Abstract: A fixture for packaging MEMS devices includes a base, a first material layer, an insulating layer and a second material layer. The base defines units, each including a notch. The first material layer is disposed on the base and the notches. The insulating layer is disposed on a part of the first material layer and exposes the other part of the first material layer located on the notches. The second material layer is disposed on the other part of the first material layer and formed with caps, whereby the caps are physically connected to the MEMS devices, and the MEMS devices are corresponding to the units of the base, wherein there is a first connecting force between the first and second material layers, there is a second connecting force between the caps and the MEMS devices, and the second connecting force is greater than the first connecting force.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: January 26, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsueh An Yang
  • SEMICONDUCTOR PACKAGE AND METHOD FOR PROCESSING AND BONDING A WIRE
    Publication number: 20100007009
    Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG, Cheng Tsung HSU, Chih Cheng HUNG
  • TRANSFORMER
    Publication number: 20100007439
    Abstract: A transformer is provided with four capacitors and four inductors. The first capacitor is electrically connected between a first port and ground in series. The first inductor is electrically connected to the first port in series. The second capacitor is electrically connected between the first inductor and ground in series. The second inductor is electrically connected between the first inductor and the second capacitor in series. The third capacitor is electrically connected between a second port and ground in series. The third inductor is electrically connected to the second port in series. The fourth capacitor is electrically connected between a third port and ground in series. The fourth inductor is electrically connected between the third inductor and the third port in series.
    Type: Application
    Filed: February 6, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Han Chen, Pao-Nan Lee, Ying-Chieh Shyu
  • BAND PASS FILTER
    Publication number: 20100007438
    Abstract: A band pass filter includes an original circuit. An interaction of at least two of components of the original circuit produces at least a mutual capacitor or at least a mutual inductor, which constitutes a resonance circuit with the original circuit to produce at least a transmission zero for increasing the attenuation rate of the stop band.
    Type: Application
    Filed: February 6, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Pao-Nan Lee, Chi-Tsung Chiu