Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
Type:
Grant
Filed:
December 30, 2014
Date of Patent:
September 6, 2016
Assignee:
ADVANCED SEMINCONDUCTOR ENGINEERING, INC.
Abstract: The present invention is related to a substrate structure and a method for fabricating the substrate, and more particularly to a substrate structure of integrated embedded passive components and a method for fabricating the substrate. In the present invention, the openings are formed on the substrate by removing part of external circuit layer and part of dielectric layer. Then, the embedded components are disposed in these openings. Therefore, the shift and short circuit of the passive components caused by the flow and gather of the solder paste in reflow or other high-temperature processes can be improved.
Type:
Application
Filed:
December 14, 2005
Publication date:
December 21, 2006
Applicant:
ADVANCED SEMINCONDUCTOR ENGINEERING, INC.
Inventors:
Ying-Chou Chen, Ying-Te Ou, Chiu-Wen Lee