Patents Assigned to Advanced Test Technologies Inc.
  • Publication number: 20090321901
    Abstract: According to example embodiments, a device configured to dissipate heat from a first chip and a second chip on a multi-chip package includes a primary heat sink configured to contact an upper surface of the first chip, a secondary heat sink configured to contact an upper surface of the second chip, the secondary heat sink disposed within the primary heat sink and movable in relation to the primary heat sink, and a thermally conductive substance disposed in contact with the primary heat sink and the secondary heat sink.
    Type: Application
    Filed: June 25, 2008
    Publication date: December 31, 2009
    Applicant: ANTARES ADVANCED TEST TECHNOLOGIES, INC.
    Inventors: Chris Lopez, Brian L. Hahn, Sudhir Kumar, Trevor J. Moody
  • Publication number: 20090261851
    Abstract: According to some example embodiments, an interconnect has a crown with contact tips, in which each of the contact tips is structured to physically contact a substantially spherical solder ball along a curved inner surface of the contact tip.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 22, 2009
    Applicant: ANTARES ADVANCED TEST TECHNOLOGIES, INC.
    Inventors: Jiachun Zhou, Praveen Matlapudi
  • Publication number: 20090237097
    Abstract: According to an example embodiment, a contact cell includes a first element that is flexible and electrically conductive, and that is structured to have at least one bend along an entire length of the first element. The contact cell further includes a second element that is flexible and electrically conductive, and that is structured to have at least one bend along an entire length of the second element. The contact cell further includes a tie that is electrically non-conductive, and that is affixed to the first element and affixed to the second element such that the first element and second element are physically and electrically separated from each other.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 24, 2009
    Applicant: ANTARES ADVANCED TEST TECHNOLOGIES, INC., a Washington corporation
    Inventors: ILAVARASAN M. PALANIAPPA, KANAPATHIPILLAI PRABAKARAN
  • Patent number: 7402051
    Abstract: An interconnect assembly is provided for electrically connecting first and second circuit members. Each of the circuit members comprises an array of electrical contacts. The interconnect assembly includes a plurality of compressible electrical conductors having opposite ends respectively configured for contacting the electrical contacts of the first and second circuit members. The interconnect assembly also includes a carrier defining a plurality of apertures for receiving the conductors and at least one retainer contacting each conductor. Each of the retainers has a maximum diameter that is greater than a minimum diameter of the apertures such that a portion of each conductor is retained within one of the apertures.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: July 22, 2008
    Assignee: Antares Advanced Test Technologies, Inc.
    Inventors: Rakesh Batish, Richard M. Pointer
  • Patent number: 7297004
    Abstract: An electrical conductor comprises a compressible conductive member and a tubular conductive sleeve, wherein the sleeve includes an internal deformation. The compressible member comprises a tubular lattice of interlaced wires received axially within the sleeve and engaged therein by the internal deformation to retain the compressible member axially within the sleeve.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: November 20, 2007
    Assignee: Antares Advanced Test Technologies, Inc.
    Inventors: John M. Shuhart, Timothy L. Kraynak
  • Patent number: 7217139
    Abstract: An interconnect assembly for providing electrical interconnection between elements of a probe card assembly is provided. The interconnect assembly includes a frame defining a plurality of openings and a plurality of conductive contacts coupled to the frame. Each of the conductive contacts includes (a) a first resilient arm extending away from a first surface of the frame and (b) a second resilient arm extending away from a second surface of the frame. At least one of the first resilient arm or the second resilient arm extends through one of the plurality of openings.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: May 15, 2007
    Assignee: Antares Advanced Test Technologies, Inc.
    Inventors: Jim Jaquette, Gene Tokraks, Steve Fahrner
  • Patent number: 5424633
    Abstract: This application describes a method of testing for manufacturing faults and quality of unpopulated or inactive populated electronic printed circuit boards (PCB). This method can be used to develop a new contactless test system (CTS). An electromagnetic field is generated by an energizing plate connected to an AC signal. When a board under test (BUT) is placed within the electromagnetic field, perturbation of the original field by conducting elements on the BUT is solely a function of the geometrical layout of the conducting elements on the BUT. Therefore, measurement of the perturbed electromagnetic field produces a characteristic pattern for the BUT. Such a pattern can then be compared to a known pattern for the same type of board to determine whether the BUT is faulty (shorts or opens) or not faulty. The most distinctive feature of this method is that testing PCBs by this method requires no electrical contact with the BUT due to the use of the energizing plate.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: June 13, 1995
    Assignee: Advanced Test Technologies Inc.
    Inventor: Jacob Soiferman
  • Patent number: 5218294
    Abstract: This application describes a novel method and its implementation for testing unpopulated and populated electronic printed circuit boards (PCBs). This method can be used to develop a new contactless test system (CTS). While eliminating drawbacks of existing test systems, this method measures electromagnetic near field distribution in the vicinity of a PCB, contactlessly, by using suitable sensors (possibly printed near field planar antennas) and sensitive measuring and processing devices. The electromagnetic fields (EMF) are generated by the distribution of charges and currents on paths and elements of the board under test (BUT). Therefore, accurate and repeatable measurements of these fields produce a specific pattern for the BUT. Such a pattern is then compared to a known pattern for the same type of board to determine whether the BUT is faulty or nonfaulty.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: June 8, 1993
    Assignee: Advanced Test Technologies Inc.
    Inventor: Jacob Soiferman