Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.
Abstract: A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.
Type:
Grant
Filed:
September 6, 2012
Date of Patent:
June 27, 2017
Assignee:
Advances Micro Devices, Inc.
Inventors:
Nam Sung Kim, James M. O'Connor, Michael J. Schulte, Vijay Janapa Reddi
Abstract: A method for scheduling activities in a manufacturing system includes defining a plurality of observed states associated with the manufacturing system. State estimates are generated for the observed states. Uncertainty values for the state estimates are generated. A plurality of candidate schedules for performing activities in the manufacturing system is identified. Changes to the uncertainty values are predicted based on the candidate schedules. One of the candidate schedules is selected based on the predicted changes to the uncertainty values.