Patents Assigned to Advantest Coporation
  • Patent number: 10575738
    Abstract: In a magnetic field measurement apparatus and a magnetic field measurement method provided herein, a magnetic field from an object is measured by a magnetic sensor group including a plurality of magnetic sensors. Then, an estimated value of a common noise component included in observed quantities of the magnetic sensors of all the channels of the magnetic sensor group is obtained as an external magnetic noise component. Finally the magnetic signal from the object is calculated by subtracting the estimated value from the observed quantity of each of the magnetic sensors.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 3, 2020
    Assignee: ADVANTEST COPORATION
    Inventors: Takeshi Tanaka, Yuji Ogata, Yoshiyuki Hata, Toshiaki Hayakawa, Tomoaki Ueda
  • Publication number: 20100014079
    Abstract: An object of the present invention is to enable a change in a frequency for which an electric signal based on an optical signal is measured by a spectrum analyzer.
    Type: Application
    Filed: June 8, 2009
    Publication date: January 21, 2010
    Applicant: ADVANTEST Coporation
    Inventors: Tomoyu YAMASHITA, Motoki IMAMURA
  • Publication number: 20090251939
    Abstract: A priority encoder encodes an (N+1)-bit thermometer code, where N indicates a natural number. A plurality of selectors are arranged in a matrix of M rows and (N+1) columns, where M indicates a natural number, and select one of signals at first and second input terminals (1,0) in accordance with the value of a signal input to the control terminal. An output signal from the selector in the i-th row and (j?1)th column is input to the first input terminal of the selector in the i-th row and j-th column (1?i?M, 2?j?N+1), a predetermined value of 1 or 0 is input to the second input terminal of the selector in the i-th row and j-th column, and the j-th significant bit of the thermometer code is input to the control terminal of the selector in the i-th row and j-th column.
    Type: Application
    Filed: March 26, 2009
    Publication date: October 8, 2009
    Applicant: Advantest Coporation
    Inventor: Shoji Kojima
  • Publication number: 20060129335
    Abstract: The test apparatus according to the present invention includes: a data sampler for acquiring a plurality of data sample values for data signals from the DUT; a data change point detection section for detecting a data change point from the sample value; a data change point storage section for writing the data change point based on CLK 1 and for reading the same based on CLK 2; a clock sampler for acquiring a plurality of clock sample values for clock signals from the DUT; a clock change point detection section for detecting a clock change point from the sample value; a clock change point storage section for writing the clock change point based on CLKs and reading the same based on CLK2; a phase difference detection section for detecting the phase difference between the data change point and the clock change point which are simultaneously read from the data change point storage section and the clock change point storage section; and a spec comparison section for comparing the phase difference with the spec to d
    Type: Application
    Filed: January 31, 2006
    Publication date: June 15, 2006
    Applicant: Advantest Coporation
    Inventor: Hirokatsu Niijima
  • Patent number: 5831989
    Abstract: There is provided a memory testing apparatus which can read out the information of failure memory cells of a tested memory from a failure analysis memory having the same memory capacity as that of a memory under test and can complete in a short time period the process for computing the classified total of the number of memory cell failures occurred. The memory area of the failure analysis memory is subdivided into a plurality of memory blocks, a flag memory having the same number of addresses as the number of the subdivided memory blocks is provided, and an address is assigned to each of the memory blocks. When a failure occurs in one of the memory blocks, a logical "1" indicating failure information is written at an address of the flag memory corresponding to that memory block.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: November 3, 1998
    Assignee: Advantest Coporation
    Inventor: Kenichi Fujisaki