Abstract: A method of reducing electromagnetic radiation through an opening for cables for an electronic device and a peripheral employs an electromagnetic radiation shield which is capable of effectively shielding electromagnetic radiation easily regardless of the number of cables and which can easily be attached and removed. A soft, electrically conductive electromagnetic radiation shield cloth is disposed in fully covering relation to an opening defined in a cabinet to allow cables to be connected to terminals of an electronic device unit. The electrically conductive cloth is attached in an electrically conductive fashion to the shielded cabinet so as to be openable and closable with respect to opening. The electrically conductive cloth has a plurality of vertical slits defined therein for passage of the cables therethrough, with a lower side of the electrically conductive cloth being a free end.

Abstract: The present invention offers a method and apparatus for measuring the waveform quality of a CDMA signal with increased accuracy. A baseband digital measuring signal Z(k) from a quadrature transform/complementary filter 22 is applied to a demodulating part 25, wherein it is demodulated by a PN code of a pilot signal to detect a bit train and an amplitude a'.sub.i. An ideal signal R.sub.i is generated from the bit train, the amplitude a'.sub.i and the PN code. At the same time, auxiliary data A, B, C, H and I, which are used to solve approximate simultaneous equations for computing parameters that minimize the square of the difference between the ideal signal R.sub.i and the measuring signal Z(k), are generated in an ideal signal/auxiliary data generating part 26. The thus obtained auxiliary data and the measuring signal Z(k) are used to solve the simultaneous equations to estimate the parameters in a parameter estimating part 27.

Abstract: An IC tester is provided which is capable of preventing the temperature of an IC heated to a predetermined temperature from falling during the test. A box-like housing 70 constructed of a thermally insulating material is mounted on a performance board PB. An IC socket SK and a socket guide 35 are accommodated in a space bounded by the box-like housing 70 and the performance board PB. A through-aperture 71 is formed in the top wall of the housing 70 for passing an IC under test carried by a movable rod 60R of a Z-axis driver into and out of the interior of the housing 70. An opening/closing plate 72 is disposed over the housing 70 for movement in a horizontal direction. This plate 72 is adapted to close the through-aperture 71 of the housing 70 when the movable rod 60R is outside of the housing to thereby maintain the interior of the box-like 70 in an almost thermally insulated condition.

Abstract: The invention relates to an objective lens for influencing a particle beam, particularly an electron beam with a magnetic single-pole lens and an electrostatic lens having a first and a second electrode which can be supplied with different potentials. The objective lens is characterized in that the electrostatic lens is disposed after the magnetic single-pole lens in the direction of the particle beam.

Abstract: The circuit arrangement of a memory testing apparatus having a ROM expected value memory is simplified. There are provided a first logical comparator 26 for logically comparing a data read out of a memory under test 200 with an expected value data from a pattern generator 11 as well as a second logical comparator 28 having its one input terminal supplied with a result of the comparison in the first logical comparator 26. The second logical comparator 28 has the other input terminal to be supplied with a ROM expected value data read out of a ROM expected value memory 16. A data read out of a RAM under test is logically compared in the first logical comparator 26 while a data read out of a ROM under test is logically compared in the second logical comparator 28.

Abstract: The invention relates to a method and apparatus for dimension measurement and inspection of structures having a high aspect ratio, wherein a corpuscular beam is directed onto an interesting feature of the structure and backscattered corpuscles and/or secondary corpuscles released by the corpuscular beam are detected and evaluated. To increase the detection efficiency surroundings of the interesting feature are removed before measurement and inspection thereof.

Abstract: Disclosed is a method of producing a block mask, which is employed in an electron-beam lithography apparatus, with high precision irrespective of the size of openings. The electron-beam lithography apparatus is of a type that produces a unit pattern at a time by transmitting an electron beam through openings selected from among a plurality of kinds of openings of a block mask, links the unit pattern with a previous one, and repeats this process to delineate a desired pattern. The method consists of four steps. At the first step, a resist is applied to the surface of a substrate of a block mask. At the next step, the resist is exposed to delineate patterns of a plurality of kinds of openings. At the next step, the exposed resist is developed. At the next step, the substrate of the block mask is etched.

Abstract: Disclosed is a waveform measuring apparatus in which an integration period T can be discretionally set to a value in accordance with the analog voltage cycle of the device being measured with a simple circuit configuration. The waveform measuring apparatus has an integrator circuit for integrating a fixed repeat-cycle analog input voltage during a period when a gate is ON and the waveform measuring apparatus converts the analog input voltage based on the integrated output of the integrator circuit.

Abstract: A handler is provided in which an operator can easily input test conditions for ICs of a lot. The handler includes a test parameter memory part, a parameter set memory part, a schedule memory part, a lot data memory part, a retest data memory part, and a control. The test parameter memory part restores, as the test conditions for the ICs to be tested of each lot, at least parameters of basic conditions of operation, parameters of classifying conditions for the tested devices, at least one parameter of socket selecting conditions in the test section, and parameters of temperature conditions for the constant temperature chamber. The parameter set memory part stores a plurality of parameter sets each set of which is a combination of parameters, one for one condition stored in the test parameter memory part. The schedule memory part stores a name of each lot, and a parameter set and a status corresponding to each lot name in testing sequence. The lot data memory part stores data of the test results for each lot.

Abstract: A semiconductor device transporting apparatus and a semiconductor device posture altering apparatus are provided which constitute a portion of a semiconductor device transporting and handling apparatus used in a semiconductor device testing apparatus of magazine/tray combination type. The semiconductor device transporting apparatus and the semiconductor device posture altering apparatus are used for loading onto a test tray in the horizontal posture semiconductor devices from a magazine supported in an inclined posture by which semiconductor devices can run out therefrom by their own weights.

Abstract: A main frame of an IC testing apparatus is formed in the shape of a horizontally elongated box with its height close to the height of wafer probers. Two wafer probers are arranged side by side transversely of the main frame on the front said thereof. One rotary drive is equipped with two output shafts which are connected via respective clutches with the rotary drive, and the testing heads are connected to the associated output shafts. The rotary drive is disposed on the top of the main frame with an extension of the upper portion of the rotary drive, and is adapted to rotatively drive the testing heads connected to the output shifts between a fist position opposing the contact section of the associated wafer prober and a second position over the top of the main frame. This construction reduces the installation areas for each of the wafer probers as well as narrowing the space between the wafer probers and the main frame.

Abstract: An IC receiving tray storage device is provided which is capable of securedly identifying the category of the tested ICs sorted for each category and received in the corresponding tray in the unloader section after end of test. Mounted to the tray storage is a casing comprising a generally rectangular base plate and a plurality of outer walls standing substantially upright and separately from each other on the base plate. A category identifying indicator is attached to at least one outer wall of the casing. This category identifying indicator indicates the category of ICs received in the tray. Also, in the base plate of the casing is formed an opening 71 through which a vertically movable unit is free to move. By the category identifying indicator, the category of the tested ICs received in the tray can be easily confirmed after the tray storage device has been taken out from the IC handler.

Abstract: A ball grid array semiconductor measuring socket is provided in which a contact pressure force to a solder ball is generated in the direction substantially orthogonal to the longitudinal direction of a forked contact pin and the length of the forked contact pin can be designed to the required minimum length independently of the contact pressure force. The forked contact pin formed by stamping out a sheet metal having a resilience into a tuning fork shape is mounted in a receiving hole formed through an insulating housing. Each forked contact pin is constructed so that the tip portions of a pair of elastic forked portions form contact portions for contacting with a solder ball 12 and that the tip portions contact with a solder ball at two points.

Abstract: A semiconductor device testing system is provided efficiently utilizes a plurality of semiconductor device testing apparatus. More particularly, a host computer controls a plurality of semiconductor device testing apparatuses and a dedicated classifying machine. A storage information memory stores storage information of each semiconductor device such as a number assigned to each tested semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and is provided in the host computer. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in a handler part of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory.

Abstract: A clock pulse transmission circuit is provided which can automatically correct, in case the duty factor of transmitted clock pulses has an error, the duty factor error. In a receiving unit 2, a pair of positive and negative clock pulses Sp and Sn transmitted from a transmitting unit 1 are inputted to a receiver 12 which outputs, in response thereto, a pair of positive and negative clock pulses V3 and V4. The DC components of these positive and negative clock pulses are taken out by a first integrator circuit and a second integrator circuit respectively to transmit them to the transmitting unit 1 through a pair of transmission lines 25 and 26, respectively. In the transmitting unit 1, a difference between the direct current levels of the respective positive and negative clock pulses is found and integrated. The integrated value is supplied to a driver 6 as a threshold voltage Vth.

Abstract: In a memory testing apparatus capable of testing both memories of a parallel input/parallel output type and a serial input/serial output type, in case of testing the serial input/serial output type memory, failure data in read out data serially outputted from the memory are separated in bit by bit basis and are stored in a failure analysis memory at different time points in the time axis so that a failure bit position can be specified. A failure multiplexer 14 for selecting and taking out outputs from a terminal of a memory under test 10 is provided in the output side of a logical comparator 13, and a bit selector 17 is provided between the failure multiplexer and a failure analysis memory 15.

Abstract: A cooler-equipped printed circuit board, in which electronic devices arranged in a matrix form on the printed circuit board are covered with a sealed case held in liquidtight contact with the board and having a coolant channel from an inlet port and an outlet port made in the case. Barriers are provided in the coolant channel to change the direction of flow of the coolant to stir it and make its temperature uniform throughout it.

Abstract: There is provided a memory testing apparatus which can complete a DC test FOR a memory in a short time period.

Abstract: With using one scanning stage 19 where a plurality of wafers 16A to 16E is mounted through wafer holders 20A to 20E and balancing stage 21 disposed below scanning stage 19, scanning stage 19 is scanned based on exposure data common to a plurality of charged particle beam exposure apparatus 10A to 10E, and balancing stage 21 is scanned so that barycenter G of scanning stage 19 and balancing stage 21 becomes a fixed point. The positions of reflecting mirrors 70L and 70R secured to stage 19 are measured and based on their values, the expansion/contraction ratio of stage 19 and the positions of samples 16A to 16E are calculated to obtain deviation of the positions from target positions. Stage 19 is modeled such that rigid areas 19A to 19E are loosely connected, and for each area, the positions of three points are measured to calculate deviation of the exposure target position due to rotation of each ridged area. These deviations are corrected by deflectors 18A to 18D.