Abstract: A circuit which controls access of host and remote processors to a single memory. A first flip-flop indicates acceptance or refusal of the processor's memory access requests. A second flip-flop provides a wait signal to the host processor when the remote processor is accessing the memory. A gating circuit causes the first flip-flop to accept the remote processor's access request when both the host and remote processors request memory access at the same time.

Abstract: Differential encoding is commonly used in data transmission systems because it allows correct recovery of the data even though the polarity may have changed during transmission. However, single errors which are introduced result in double errors, i.e., error of an even number following the differential decoding process. Because many error detection schemes rely upon parity checks, which look for an odd number to determine if an error has occurred, the conversion of the single error to a double error means that single errors normally would not be detected. A precoder is used to introduce correlation by modulo two addition of the precoded present digit with a selected combination of past digits. The differential decoder will still provide double errors but a subsequent decoder, which reverses the precoding process, at least partially changes double errors into errors of an odd number.

Abstract: A parallel cyclic redundancy checking circuit which determines the validity of digital, binary, cyclical data. The parallel structure of this circuit enables it to check high frequency data. Shift registers are used to store sequentially occurring parallel groups of data and a feedback network comprising exclusive-or gates provide a coding arrangement which produces a resultant data pattern to indicate the validity of the cyclical parallel input data.

Abstract: An improved method of manufacturing a printed wiring board having the characteristics of one with a solder mask over bare copper for circuit traces and ground planes. The method includes the step of electroplating a very thin coating of tin-lead over the circuit traces, ground planes, holes and circuit pads prior to selectively coating only the pads and holes with a relatively thick coating of tin-lead solder plate. After removing the plating resist which defines the areas for selective solder coating, the board is chemically etched and then mechanically scrubbed to roughen the surface of and reduce the thickness of the thin solder plate. A solder mask may be applied over circuit traces and ground planes prior to reflowing the thick coating of solder plate. Assembled printed wiring boards may then be wave soldered without wrinkling of the solder mask.

Abstract: Apparatus for synchronizing the frequency of locally generated pilot signals with those of remotely generated pilot signals where frequency errors are introduced during transmission. A pair of demodulated pilot signals F1' and F2' are filtered and mixed to derive a third signal having a frequency equal to F2'-F1'. The difference frequency has no frequency error component so the third signal is used in a phase locked loop to regenerate a reference frequency (fr) signal.Two methods are disclosed to extract a control signal which is proportional to the error frequency. In one embodiment one of the received pilots (F1') is divided in frequency by 1/k1 and then subtracted from fr to yield 1/k1 times the error frequency df. By integrating this signal it becomes usable as an AFC signal to control a local oscillator.

Abstract: Two pilot signals, derived so that there is a predetermined ratio between the frequency difference of the tones and the absolute frequency of either of the pilot signals, are transmitted from a reference station to each of a number of remote stations. At each receiving station, the frequency error is derived from the frequency difference of the two pilot signals, and this frequency error is used to adjust the frequency of the local oscillator.

Abstract: A parallel cyclic redundancy checking circuit which determines the validity of digital, binary, cyclical data. The parallel structure of this circuit enables it to check high frequency data. Shift registers store sequentially occurring parallel groups of data and a feedback network comprising exclusive-or gates provides a coding arrangement which produces a resultant data pattern to indicate the validity of the cyclical parallel input data. Resultant data patterns are periodically stored in a random-access-memory which initializes the shift registers to provide a time sharing operation. A comparator detects invalid data by comparing the resultant patterns with expected values.

Abstract: The present invention relates to an automatic meter reading transponder. The transponder is comprised of a receiver for receiving an external instruction and a transmitter for transmitting data. A CPU is connected to the receiver and the transmitter. A ROM is connected to the CPU and ROM contains a program for controlling the operation of the CPU. A real time clock is connected to the CPU for determining sequential predetermined time periods. Three input terminals are connected to the CPU for receiving data to be stored in a RAM. One of the three input terminals has pulses impressed thereon, the number of pulses being representative of electric power consumption. The one input terminal is also connected, via the CPU to a time-of-day memory.