Abstract: This disclosure provides methods, devices, and systems for generating clock signals. The present implementations more specifically relate to generating multiple clock signals having different frequencies using a single piezoelectric resonator. In some aspects, a clock generator, including a piezoelectric resonator coupled to a voltage amplifier in a feedback network, may be operable in a high-performance mode and a low-power mode. When operating in the high-performance mode, the clock generator may produce a high frequency clock signal and a low frequency clock signal using the same piezoelectric resonator. In some implementations, the high frequency clock signal may be produced by a buffer amplifier coupled to an output of the voltage amplifier and the low frequency clock signal may be produced by a frequency divider coupled to the output of the voltage amplifier. When operating in the low-power mode, the clock generator produces only the low-frequency clock signal via the frequency divider.

Abstract: This disclosure provides methods, devices, and systems for timestamping Ethernet packets. The present implementations more specifically relate to capturing timestamps in the same clock domain as a media-dependent interface (MDI). In some aspects, a physical layer (PHY) transceiver may generate a receive (RX) timestamp for a precision time protocol (PTP) packet based on a time at which a physical medium attachment (PMA) sublayer outputs, to a physical coding sublayer (PCS), one or more PHY frames carrying the PTP packet. In some other aspects, a PHY transceiver may generate a transmit (TX) timestamp for a PTP packet based on a time at which a PCS outputs a reference frame to a PMA sublayer, where the reference frame precedes one or more PHY frames carrying the PTP packet.

Abstract: This disclosure provides methods, devices, and systems for wireline communications. The present implementations more specifically relate to line driver circuits that support differential and single-ended signaling. In some aspects, a line driver circuit may include a pair of transmit (TX) digital-to-analog converters (DACs) and a “mock” TX DAC. When operating in a differential mode, the line driver circuit uses both TX DACs to drive a primary data signal and a complementary data signal onto a differential transmission line. When operating in a single-ended mode, the line driver circuit uses only one of the TX DACs to drive the primary data signal onto a single-ended transmission line and converts the complementary data signal to a mock echo signal via the mock TX DAC, where the mock echo signal mimics an echo of the complementary data signal. The mock echo signal may cancel echoes associated with the primary data signal.

Abstract: This disclosure provides methods, devices, and systems for wireline communications. The present implementations more specifically relate to line driver circuits that support differential and single-ended signaling. In some aspects, a line driver circuit may include a pair of transmit (TX) digital-to-analog converters (DACs) and a “mock” TX DAC. When operating in a differential mode, the line driver circuit uses both TX DACs to drive a primary data signal and a complementary data signal onto a differential transmission line. When operating in a single-ended mode, the line driver circuit uses only one of the TX DACs to drive the primary data signal onto a single-ended transmission line and converts the complementary data signal to a mock echo signal via the mock TX DAC, where the mock echo signal mimics an echo of the complementary data signal. The mock echo signal may cancel echoes associated with the primary data signal.

Abstract: Methods and apparatus for reducing mode conversion associated with differential signals are disclosed. An example method includes providing a common mode dither signal between a first terminal and a second terminal associated with a differential signal, generating a correlation signal representing a correlation of the common mode dither signal and the differential signal, and selectively incrementing a first capacitive loading at the first terminal or a second capacitive loading at the second terminal based at least in part on the correlation signal.

Abstract: Methods and apparatus for processing signals captured by one or more sensors are disclosed. An example method includes receiving a first signal from a control circuit, the first signal including control data associated with the one or more sensors, recovering a fixed frequency clock signal and a control signal from the first signal, generating a spread spectrum clock signal based on the fixed frequency clock signal, receiving a sensor data signal based at least in part on data captured by the one or more sensors, the spread spectrum clock signal, and the control signal, retiming the sensor data signal based at least in part on the spread spectrum clock signal and the fixed frequency clock signal, and generating an output signal based on the retimed sensor data signal.