Abstract: A cryptographic accelerator (1) has a host interface (2) for interfacing with a host sending cryptographic requests and receiving results. A CPU (3) manages the internal logical unit in an exponentiation sub-system (7) having modulator exponentiators (30). The exponentiators (30) are chained together up to a maximum of four, in a block (20). There are ten blocks (20). A scheduler uses control registers and an input buffer to perform the scheduling control.
Type:
Grant
Filed:
April 11, 2002
Date of Patent:
November 8, 2005
Assignee:
AEP Systems Limited
Inventors:
Christopher Fairclough, Francis Flanagan