Patents Assigned to aeris CAPITAL Sustainable IP Ltd.
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Patent number: 9053938Abstract: Methods and devices are provided for forming a low-resistance, high light transmission layer. In one embodiment of the present invention, a method is provided comprised of creating a plurality of vias on a substrate, the vias formed in material that has a maximum processing temperature that less than a pre-defined threshold; adding a plurality of electrically conductive material into the vias; and solution depositing a nanowires infused window layer that has a first thickness at certain areas and a second thickness at other areas, wherein overall sheet resistance is between about 1 to 10 ohms per square, while light transmission combined is at least 70% and creates less than 5% shadow loss. The method may involve using a transparent conductive oxide layer beneath the window layer. This can create a layer that eliminates opaque bus bars or fingers associated with traditional solar cells. This may be an all-solution deposited process using only one deposition set or multiple deposition steps.Type: GrantFiled: October 8, 2010Date of Patent: June 9, 2015Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: Hak Fei Poon, Tianyue Yu
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Patent number: 8969717Abstract: Methods and devices for increase power output from solar devices. In one embodiment, the technique enables the front hot solar panel surface to be cooled by attachment of a thermoelectric multilayer stack to the back solar panel surface. The thermoelectric stack cools the solar panel front surface by drawing heat from the front to the back of the panel. That heat is transformed into mechanical vibrations using an inverse Peltier effect and that mechanical energy then transformed into electrical energy using a piezoelectric effect. Power output is first increased by lower operating temperature on front, resulting in a higher power conversion efficiency for the photovoltaic effect taking place in the CIGS/CdS active layers or other thin films, then from an additional power output from secondary electrical energy created from mechanical arising from the temperature-gradient driven occurrence of the thermoelectric effect.Type: GrantFiled: August 12, 2011Date of Patent: March 3, 2015Assignee: aeris CAPITAL Sustainable IP Ltd.Inventor: Brian M. Sager
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Patent number: 8941001Abstract: Methods and devices are provided for improved anti-reflective texture. In some embodiments, the absorber layer for use with this anti-reflective layer is a group IB-IIIA-VIA absorber layer.Type: GrantFiled: November 17, 2010Date of Patent: January 27, 2015Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: Louis Basel, Robert Stancel, Christian Fessenmaier
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Patent number: 8927315Abstract: Methods and devices are provided for high-efficiency solar cells. In one embodiment, an assembly is provided comprising of a plurality of solar cells each having at least one transparent conductor, a photovoltaic layer, at least one bottom electrode, a plurality of emitter wrap through (EWT) vias containing a conductive material, and a plurality of series interconnect vias containing a conductive material. The assembly may also include a backside support coupled to the solar cells, wherein the backside support is patterned to have electrically conductive areas and electrically nonconductive areas that create a series interconnect between solar cells electrically coupled by the support and prevents parallel connections between the solar cells. The cells may have a via insulating layer in each via separating the conductive material in each via from any side walls of the bottom electrode.Type: GrantFiled: July 31, 2012Date of Patent: January 6, 2015Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: James R. Sheats, Werner Dumanski
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Patent number: 8889469Abstract: Methods and devices are provided for forming multi-nary semiconductor. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur, forming a senary or higher semiconductor alloy. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: June 26, 2012Date of Patent: November 18, 2014Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: David B. Jackrel, Katherine Dickey, Kristin Pollock, Jacob Woodruff, Peter Stone, Gregory Brown
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Patent number: 8846141Abstract: Methods and devices are provided for high-throughput printing of semiconductor precursor layer from microflake particles. In one embodiment, the method comprises of transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be microflakes that have a high aspect ratio. The resulting dense film formed from microflakes are particularly useful in forming photovoltaic devices.Type: GrantFiled: July 18, 2008Date of Patent: September 30, 2014Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: Matthew R. Robinson, Jeroen K. J. Van Duren, Craig Leidholm, Brian M. Sager
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Patent number: 8809678Abstract: CIGS absorber layers fabricated using coated semiconducting nanoparticles and/or quantum dots are disclosed. Core nanoparticles and/or quantum dots containing one or more elements from group 13 and/or IIIA and/or VIA may be coated with one or more layers containing elements group IB, IIIA or VIA. Using nanoparticles with a defined surface area, a layer thickness could be tuned to give the proper stoichiometric ratio, and/or crystal phase, and/or size, and/or shape. The coated nanoparticles could then be placed in a dispersant for use as an ink, paste, or paint. By appropriate coating of the core nanoparticles, the resulting coated nanoparticles can have the desired elements intermixed within the size scale of the nanoparticle, while the phase can be controlled by tuning the stoichiometry, and the stoichiometry of the coated nanoparticle may be tuned by controlling the thickness of the coating(s).Type: GrantFiled: May 7, 2012Date of Patent: August 19, 2014Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: Brian M. Sager, Dong Yu, Matthew R. Robinson
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Patent number: 8729543Abstract: Methods and devices are provided for forming multi-nary semiconductor. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur, forming a senary or higher semiconductor alloy.Type: GrantFiled: August 11, 2011Date of Patent: May 20, 2014Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: David B. Jackrel, Katherine Dickey, Kristin Pollock, Jacob Woodruff, Peter Stone, Gregory Brown
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Patent number: 8722160Abstract: An inorganic/organic hybrid nanolaminate barrier film has a plurality of layers of an inorganic material that alternate with a plurality of layers of an organic material. Such a barrier film can be fabricated using nanocomposite self-assembly techniques based on sol-gel chemistry.Type: GrantFiled: October 31, 2003Date of Patent: May 13, 2014Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: Brian M. Sager, Martin R. Roscheisen
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Patent number: 8697981Abstract: Methods and devices are provided for improved large-scale solar installations. In one embodiment, a photovoltaic module is provided comprising a module front layer comprising a glass plate, a module back layer comprising an electrically conductive foil, and a plurality of solar cells arranged to be protected by the front layer and the back layer. In some embodiments, the module back layer is aluminum foil. The module back layer may have an externally exposed surface. The module back layer may be electrically grounded. An electrically insulating pottant material may be used with the solar cells to separate them from the module back layer. This allows for a high voltage withstand between the cells and the outer surface of the back layer.Type: GrantFiled: February 27, 2008Date of Patent: April 15, 2014Assignee: aeris CAPITAL Sustainable IP Ltd.Inventors: Paul M. Adriani, Martin R. Roscheisen, Jeremy H. Scholz